[Mesa-dev] [PATCH 52/57] i965/vec4: Assign correct destination offset to rewritten instruction in register coalesce.

[Francisco Jerez]

Because the pass already checks that the destination offset of each
'scan_inst' that needs to be rewritten matches 'inst->src[0].offset'
exactly, the final offset of the rewritten instruction is just the
original destination offset of the copy.  This is in preparation for
adding support for sub-GRF offsets to the VEC4 IR.
---
 src/mesa/drivers/dri/i965/brw_vec4.cpp | 3 +--
 1 file changed, 1 insertion(+), 2 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/brw_vec4.cpp b/src/mesa/drivers/dri/i965/brw_vec4.cpp
index 8f8d262..470f814 100644
--- a/src/mesa/drivers/dri/i965/brw_vec4.cpp
+++ b/src/mesa/drivers/dri/i965/brw_vec4.cpp
@@ -1254,8 +1254,7 @@ vec4_visitor::opt_register_coalesce()
                                     inst->src[0].swizzle);
 	       scan_inst->dst.file = inst->dst.file;
                scan_inst->dst.nr = inst->dst.nr;
-	       scan_inst->dst.offset = scan_inst->dst.offset % REG_SIZE +
-                  ROUND_DOWN_TO(inst->dst.offset, REG_SIZE);
+	       scan_inst->dst.offset = inst->dst.offset;
                if (inst->saturate &&
                    inst->dst.type != scan_inst->dst.type) {
                   /* If we have reached this point, scan_inst is a non
-- 
2.9.0