[Mesa-dev] [PATCH] gm107/ir: allow indirect inputs to be loaded by frag shader

[Ilia Mirkin]

Looks like the GM107 IPA op does not allow a separate offset when
using an indirect register. Instead generate an add when legalizing the
SSA. (Ideally such lowering would be done earlier, but there are opt
passes that might attempt to stuff an offset directly into such an
access.)

Signed-off-by: Ilia Mirkin <imirkin at alum.mit.edu>
---

Untested. Samuel, perhaps you can give it a whirl? Pretty sure there are
piglits that exercise this. But it should also be easy to write one.

 .../nouveau/codegen/nv50_ir_lowering_gm107.cpp     | 24 ++++++++++++++++++++++
 .../nouveau/codegen/nv50_ir_lowering_gm107.h       |  1 +
 src/gallium/drivers/nouveau/nvc0/nvc0_screen.c     |  2 +-
 3 files changed, 26 insertions(+), 1 deletion(-)

diff --git a/src/gallium/drivers/nouveau/codegen/nv50_ir_lowering_gm107.cpp b/src/gallium/drivers/nouveau/codegen/nv50_ir_lowering_gm107.cpp
index 84ef4e0..68261e6 100644
--- a/src/gallium/drivers/nouveau/codegen/nv50_ir_lowering_gm107.cpp
+++ b/src/gallium/drivers/nouveau/codegen/nv50_ir_lowering_gm107.cpp
@@ -61,10 +61,34 @@ GM107LegalizeSSA::handlePFETCH(Instruction *i)
    i->setSrc(1, NULL);
 }
 
+void
+GM107LegalizeSSA::handleINTERP(Instruction *i)
+{
+   Value *rel, *addr;
+   int offset = i->src(0).get()->reg.data.offset;
+
+   if (!i->src(0).isIndirect(0) || !offset)
+      return;
+
+   bld.setPosition(i, false);
+   rel = bld.getSSA();
+   addr = cloneShallow(func, i->src(0).get());
+   addr->reg.data.offset = 0;
+
+   bld.mkOp2(OP_ADD, TYPE_U32, addr, i->getIndirect(0, 0), bld.mkImm(offset));
+
+   i->setSrc(0, addr);
+   i->setIndirect(0, 0, rel);
+}
+
 bool
 GM107LegalizeSSA::visit(Instruction *i)
 {
    switch (i->op) {
+   case OP_LINTERP:
+   case OP_PINTERP:
+      handleINTERP(i);
+      break;
    case OP_PFETCH:
       handlePFETCH(i);
       break;
diff --git a/src/gallium/drivers/nouveau/codegen/nv50_ir_lowering_gm107.h b/src/gallium/drivers/nouveau/codegen/nv50_ir_lowering_gm107.h
index 81749bf..9ef65b9 100644
--- a/src/gallium/drivers/nouveau/codegen/nv50_ir_lowering_gm107.h
+++ b/src/gallium/drivers/nouveau/codegen/nv50_ir_lowering_gm107.h
@@ -20,6 +20,7 @@ class GM107LegalizeSSA : public NVC0LegalizeSSA
 private:
    virtual bool visit(Instruction *);
 
+   void handleINTERP(Instruction *);
    void handlePFETCH(Instruction *);
 };
 
diff --git a/src/gallium/drivers/nouveau/nvc0/nvc0_screen.c b/src/gallium/drivers/nouveau/nvc0/nvc0_screen.c
index 0627f3d..6e62d42 100644
--- a/src/gallium/drivers/nouveau/nvc0/nvc0_screen.c
+++ b/src/gallium/drivers/nouveau/nvc0/nvc0_screen.c
@@ -351,7 +351,7 @@ nvc0_screen_get_shader_param(struct pipe_screen *pscreen, unsigned shader,
    case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR:
       return shader != PIPE_SHADER_FRAGMENT;
    case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR:
-      return shader != PIPE_SHADER_FRAGMENT || class_3d < GM107_3D_CLASS;
+      return 1;
    case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR:
    case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR:
       return 1;
-- 
2.7.3