[Mesa-dev] [PATCH 7/7] radeonsi: fix FP64 UBO loads with indirect uniform block indexing

[Marek Olšák]

From: Marek Olšák <marek.olsak at amd.com>

No known tests.

Cc: mesa-stable at lists.freedesktop.org
---
 src/gallium/drivers/radeonsi/si_shader.c | 3 +--
 1 file changed, 1 insertion(+), 2 deletions(-)

diff --git a/src/gallium/drivers/radeonsi/si_shader.c b/src/gallium/drivers/radeonsi/si_shader.c
index 6d30d1c..be6fae7 100644
--- a/src/gallium/drivers/radeonsi/si_shader.c
+++ b/src/gallium/drivers/radeonsi/si_shader.c
@@ -1917,22 +1917,21 @@ static LLVMValueRef fetch_constant(
 	if (!tgsi_type_is_64bit(type))
 		result = bitcast(bld_base, type, result);
 	else {
 		LLVMValueRef addr2, result2;
 		addr2 = ctx->radeon_bld.soa.addr[ireg->Index][ireg->Swizzle + 1];
 		addr2 = LLVMBuildLoad(base->gallivm->builder, addr2, "load addr reg2");
 		addr2 = lp_build_mul_imm(&bld_base->uint_bld, addr2, 16);
 		addr2 = lp_build_add(&bld_base->uint_bld, addr2,
 				     lp_build_const_int32(base->gallivm, idx * 4));
 
-		result2 = buffer_load_const(ctx, ctx->const_buffers[buf],
-					    addr2);
+		result2 = buffer_load_const(ctx, bufp, addr2);
 
 		result = radeon_llvm_emit_fetch_64bit(bld_base, type,
 						      result, result2);
 	}
 	return result;
 }
 
 /* Upper 16 bits must be zero. */
 static LLVMValueRef si_llvm_pack_two_int16(struct gallivm_state *gallivm,
 					   LLVMValueRef val[2])
-- 
2.7.4