[Mesa-dev] [PATCH 6/9] squash! gallivm/llvmpipe: add support for ARB_gpu_shader_int64.
Nicolai Hähnle
nhaehnle at gmail.com
Fri Sep 16 13:48:38 UTC 2016
From: Nicolai Hähnle <nicolai.haehnle at amd.com>
- PIPE_CAP_INT64 is not there yet
- restrict DIV/MOD defaults to the CPU, as for 32 bits
---
src/gallium/auxiliary/gallivm/lp_bld_tgsi_action.c | 17 ++++++++---------
src/gallium/drivers/llvmpipe/lp_screen.c | 1 -
2 files changed, 8 insertions(+), 10 deletions(-)
diff --git a/src/gallium/auxiliary/gallivm/lp_bld_tgsi_action.c b/src/gallium/auxiliary/gallivm/lp_bld_tgsi_action.c
index ad512e9..010ad9d 100644
--- a/src/gallium/auxiliary/gallivm/lp_bld_tgsi_action.c
+++ b/src/gallium/auxiliary/gallivm/lp_bld_tgsi_action.c
@@ -1099,21 +1099,21 @@ u64mul_emit(
const struct lp_build_tgsi_action * action,
struct lp_build_tgsi_context * bld_base,
struct lp_build_emit_data * emit_data)
{
emit_data->output[emit_data->chan] = lp_build_mul(&bld_base->uint64_bld,
emit_data->args[0], emit_data->args[1]);
}
/* TGSI_OPCODE_U64MOD */
static void
-u64mod_emit(
+u64mod_emit_cpu(
const struct lp_build_tgsi_action * action,
struct lp_build_tgsi_context * bld_base,
struct lp_build_emit_data * emit_data)
{
LLVMBuilderRef builder = bld_base->base.gallivm->builder;
LLVMValueRef div_mask = lp_build_cmp(&bld_base->uint64_bld,
PIPE_FUNC_EQUAL, emit_data->args[1],
bld_base->uint64_bld.zero);
/* We want to make sure that we never divide/mod by zero to not
* generate sigfpe. We don't want to crash just because the
@@ -1124,21 +1124,21 @@ u64mod_emit(
LLVMValueRef result = lp_build_mod(&bld_base->uint64_bld,
emit_data->args[0], divisor);
/* umod by zero doesn't have a guaranteed return value chose -1 for now. */
emit_data->output[emit_data->chan] = LLVMBuildOr(builder,
div_mask,
result, "");
}
/* TGSI_OPCODE_MOD (CPU Only) */
static void
-i64mod_emit(
+i64mod_emit_cpu(
const struct lp_build_tgsi_action * action,
struct lp_build_tgsi_context * bld_base,
struct lp_build_emit_data * emit_data)
{
LLVMBuilderRef builder = bld_base->base.gallivm->builder;
LLVMValueRef div_mask = lp_build_cmp(&bld_base->uint64_bld,
PIPE_FUNC_EQUAL, emit_data->args[1],
bld_base->uint64_bld.zero);
/* We want to make sure that we never divide/mod by zero to not
* generate sigfpe. We don't want to crash just because the
@@ -1149,21 +1149,21 @@ i64mod_emit(
LLVMValueRef result = lp_build_mod(&bld_base->int64_bld,
emit_data->args[0], divisor);
/* umod by zero doesn't have a guaranteed return value chose -1 for now. */
emit_data->output[emit_data->chan] = LLVMBuildOr(builder,
div_mask,
result, "");
}
/* TGSI_OPCODE_U64DIV */
static void
-u64div_emit(
+u64div_emit_cpu(
const struct lp_build_tgsi_action * action,
struct lp_build_tgsi_context * bld_base,
struct lp_build_emit_data * emit_data)
{
LLVMBuilderRef builder = bld_base->base.gallivm->builder;
LLVMValueRef div_mask = lp_build_cmp(&bld_base->uint64_bld,
PIPE_FUNC_EQUAL, emit_data->args[1],
bld_base->uint64_bld.zero);
/* We want to make sure that we never divide/mod by zero to not
@@ -1175,21 +1175,21 @@ u64div_emit(
LLVMValueRef result = LLVMBuildUDiv(builder,
emit_data->args[0], divisor, "");
/* udiv by zero is guaranteed to return 0xffffffff at least with d3d10 */
emit_data->output[emit_data->chan] = LLVMBuildOr(builder,
div_mask,
result, "");
}
/* TGSI_OPCODE_I64DIV */
static void
-i64div_emit(
+i64div_emit_cpu(
const struct lp_build_tgsi_action * action,
struct lp_build_tgsi_context * bld_base,
struct lp_build_emit_data * emit_data)
{
LLVMBuilderRef builder = bld_base->base.gallivm->builder;
LLVMValueRef div_mask = lp_build_cmp(&bld_base->int64_bld,
PIPE_FUNC_EQUAL, emit_data->args[1],
bld_base->int64_bld.zero);
/* We want to make sure that we never divide/mod by zero to not
@@ -1373,24 +1373,20 @@ lp_set_default_actions(struct lp_build_tgsi_context * bld_base)
bld_base->op_actions[TGSI_OPCODE_F2D].emit = f2d_emit;
bld_base->op_actions[TGSI_OPCODE_I2D].emit = i2d_emit;
bld_base->op_actions[TGSI_OPCODE_U2D].emit = u2d_emit;
bld_base->op_actions[TGSI_OPCODE_DMAD].emit = dmad_emit;
bld_base->op_actions[TGSI_OPCODE_DRCP].emit = drcp_emit;
bld_base->op_actions[TGSI_OPCODE_DFRAC].emit = dfrac_emit;
bld_base->op_actions[TGSI_OPCODE_U64MUL].emit = u64mul_emit;
- bld_base->op_actions[TGSI_OPCODE_U64MOD].emit = u64mod_emit;
- bld_base->op_actions[TGSI_OPCODE_I64MOD].emit = i64mod_emit;
- bld_base->op_actions[TGSI_OPCODE_U64DIV].emit = u64div_emit;
- bld_base->op_actions[TGSI_OPCODE_I64DIV].emit = i64div_emit;
bld_base->op_actions[TGSI_OPCODE_F2I64].emit = f2i64_emit;
bld_base->op_actions[TGSI_OPCODE_F2U64].emit = f2u64_emit;
bld_base->op_actions[TGSI_OPCODE_D2I64].emit = f2i64_emit;
bld_base->op_actions[TGSI_OPCODE_D2U64].emit = f2u64_emit;
bld_base->op_actions[TGSI_OPCODE_I2I64].emit = i2i64_emit;
bld_base->op_actions[TGSI_OPCODE_I2U64].emit = i2u64_emit;
@@ -2684,16 +2680,19 @@ lp_set_default_actions_cpu(
bld_base->op_actions[TGSI_OPCODE_U64SGE].emit = u64sge_emit_cpu;
bld_base->op_actions[TGSI_OPCODE_I64SLT].emit = i64slt_emit_cpu;
bld_base->op_actions[TGSI_OPCODE_I64SGE].emit = i64sge_emit_cpu;
bld_base->op_actions[TGSI_OPCODE_U64MIN].emit = u64min_emit_cpu;
bld_base->op_actions[TGSI_OPCODE_U64MAX].emit = u64max_emit_cpu;
bld_base->op_actions[TGSI_OPCODE_I64MIN].emit = i64min_emit_cpu;
bld_base->op_actions[TGSI_OPCODE_I64MAX].emit = i64max_emit_cpu;
bld_base->op_actions[TGSI_OPCODE_U64ADD].emit = u64add_emit_cpu;
-
+ bld_base->op_actions[TGSI_OPCODE_U64MOD].emit = u64mod_emit_cpu;
+ bld_base->op_actions[TGSI_OPCODE_I64MOD].emit = i64mod_emit_cpu;
+ bld_base->op_actions[TGSI_OPCODE_U64DIV].emit = u64div_emit_cpu;
+ bld_base->op_actions[TGSI_OPCODE_I64DIV].emit = i64div_emit_cpu;
bld_base->op_actions[TGSI_OPCODE_U64SHL].emit = u64shl_emit_cpu;
bld_base->op_actions[TGSI_OPCODE_I64SHR].emit = i64shr_emit_cpu;
bld_base->op_actions[TGSI_OPCODE_U64SHR].emit = u64shr_emit_cpu;
}
diff --git a/src/gallium/drivers/llvmpipe/lp_screen.c b/src/gallium/drivers/llvmpipe/lp_screen.c
index c1e191b..18837a2 100644
--- a/src/gallium/drivers/llvmpipe/lp_screen.c
+++ b/src/gallium/drivers/llvmpipe/lp_screen.c
@@ -286,21 +286,20 @@ llvmpipe_get_param(struct pipe_screen *screen, enum pipe_cap param)
return 0;
case PIPE_CAP_CLIP_HALFZ:
return 1;
case PIPE_CAP_VERTEXID_NOBASE:
return 0;
case PIPE_CAP_POLYGON_OFFSET_CLAMP:
case PIPE_CAP_TEXTURE_FLOAT_LINEAR:
case PIPE_CAP_TEXTURE_HALF_FLOAT_LINEAR:
return 1;
case PIPE_CAP_CULL_DISTANCE:
- case PIPE_CAP_INT64:
return 1;
case PIPE_CAP_COPY_BETWEEN_COMPRESSED_AND_PLAIN_FORMATS:
return 1;
case PIPE_CAP_MULTISAMPLE_Z_RESOLVE:
case PIPE_CAP_RESOURCE_FROM_USER_MEMORY:
case PIPE_CAP_DEVICE_RESET_STATUS_QUERY:
case PIPE_CAP_MAX_SHADER_PATCH_VARYINGS:
case PIPE_CAP_DEPTH_BOUNDS_TEST:
case PIPE_CAP_TGSI_TXQS:
case PIPE_CAP_FORCE_PERSAMPLE_INTERP:
--
2.7.4
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