[Mesa-dev] [PATCH] i965/ir: Test thread dispatch packing assumptions.

[Jason Ekstrand]

On Sep 20, 2016 12:49 AM, "Francisco Jerez" <currojerez at riseup.net> wrote:
>
> Not intended for upstream.

If we're going to upstream this, we should remove the content saying we
won't.

Otherwise r-b

> Should cause a GPU hang if some thread is
> executed with a non-contiguous dispatch mask breaking assumptions of
> brw_stage_has_packed_dispatch().  Doesn't cause any CTS, DEQP or
> Piglit regressions, while replacing brw_stage_has_packed_dispatch()
> with a dummy implementation that unconditionally returns true on top
> of this patch causes multiple GPU hangs.
>
> v2: Drop VEC4 test and clean up slightly for upstream (Jason).
> ---
>  src/mesa/drivers/dri/i965/brw_fs.cpp | 30 ++++++++++++++++++++++++++++++
>  1 file changed, 30 insertions(+)
>
> diff --git a/src/mesa/drivers/dri/i965/brw_fs.cpp
b/src/mesa/drivers/dri/i965/brw_fs.cpp
> index 03d4f5f..c5fa3f7 100644
> --- a/src/mesa/drivers/dri/i965/brw_fs.cpp
> +++ b/src/mesa/drivers/dri/i965/brw_fs.cpp
> @@ -6832,3 +6832,33 @@ brw_compile_cs(const struct brw_compiler
*compiler, void *log_data,
>
>     return g.get_assembly(final_assembly_size);
>  }
> +
> +/**
> + * Test the dispatch mask packing assumptions of
> + * brw_stage_has_packed_dispatch().  Call this from e.g. the top of
> + * fs_visitor::emit_nir_code() to cause a GPU hang if any shader
invocation is
> + * executed with an unexpected dispatch mask.
> + */
> +static UNUSED void
> +brw_fs_test_dispatch_packing(const fs_builder &bld)
> +{
> +   const gl_shader_stage stage = bld.shader->stage;
> +
> +   if (brw_stage_has_packed_dispatch(bld.shader->devinfo, stage,
> +                                     bld.shader->stage_prog_data)) {
> +      const fs_builder ubld = bld.exec_all().group(1, 0);
> +      const fs_reg tmp = component(bld.vgrf(BRW_REGISTER_TYPE_UD), 0);
> +      const fs_reg mask = (stage == MESA_SHADER_FRAGMENT ?
brw_vmask_reg() :
> +                           brw_dmask_reg());
> +
> +      ubld.ADD(tmp, mask, brw_imm_ud(1));
> +      ubld.AND(tmp, mask, tmp);
> +
> +      /* This will loop forever if the dispatch mask doesn't have the
expected
> +       * form '2^n-1', in which case tmp will be non-zero.
> +       */
> +      bld.emit(BRW_OPCODE_DO);
> +      bld.CMP(bld.null_reg_ud(), tmp, brw_imm_ud(0), BRW_CONDITIONAL_NZ);
> +      set_predicate(BRW_PREDICATE_NORMAL, bld.emit(BRW_OPCODE_WHILE));
> +   }
> +}
> --
> 2.9.0
>
-------------- next part --------------
An HTML attachment was scrubbed...
URL: <https://lists.freedesktop.org/archives/mesa-dev/attachments/20160920/24494577/attachment-0001.html>