[Mesa-dev] [PATCH v4 3/7] intel/isl: Allow creation of 1-D compressed textures

[Jason Ekstrand]

Compressed 1-D textures are not well-defined thing in either GL or Vulkan.
However, auxiliary surfaces are treated as compressed textures in ISL and
we can do HiZ and CCS with 1-D so we need to be able to create them.  In
order to prevent actually using them (the docs say no), we assert in the
state setup code.

Signed-off-by: Jason Ekstrand <jason at jlekstrand.net>
---
 src/intel/isl/isl.c               | 12 +++++++-----
 src/intel/isl/isl_surface_state.c |  9 +++++++++
 2 files changed, 16 insertions(+), 5 deletions(-)

diff --git a/src/intel/isl/isl.c b/src/intel/isl/isl.c
index a75fddf..710c990 100644
--- a/src/intel/isl/isl.c
+++ b/src/intel/isl/isl.c
@@ -518,7 +518,6 @@ isl_calc_phys_level0_extent_sa(const struct isl_device *dev,
       assert(info->height == 1);
       assert(info->depth == 1);
       assert(info->samples == 1);
-      assert(!isl_format_is_compressed(info->format));
 
       switch (dim_layout) {
       case ISL_DIM_LAYOUT_GEN4_3D:
@@ -527,8 +526,8 @@ isl_calc_phys_level0_extent_sa(const struct isl_device *dev,
       case ISL_DIM_LAYOUT_GEN9_1D:
       case ISL_DIM_LAYOUT_GEN4_2D:
          *phys_level0_sa = (struct isl_extent4d) {
-            .w = info->width,
-            .h = 1,
+            .w = isl_align_npot(info->width, fmtl->bw),
+            .h = fmtl->bh,
             .d = 1,
             .a = info->array_len,
          };
@@ -757,7 +756,7 @@ isl_calc_phys_slice0_extent_sa_gen9_1d(
 {
    MAYBE_UNUSED const struct isl_format_layout *fmtl = isl_format_get_layout(info->format);
 
-   assert(phys_level0_sa->height == 1);
+   assert(phys_level0_sa->height == fmtl->bh);
    assert(phys_level0_sa->depth == 1);
    assert(info->samples == 1);
    assert(image_align_sa->w >= fmtl->bw);
@@ -1567,9 +1566,12 @@ get_image_offset_sa_gen9_1d(const struct isl_surf *surf,
                             uint32_t *x_offset_sa,
                             uint32_t *y_offset_sa)
 {
+   MAYBE_UNUSED const struct isl_format_layout *fmtl =
+      isl_format_get_layout(surf->format);
+
    assert(level < surf->levels);
    assert(layer < surf->phys_level0_sa.array_len);
-   assert(surf->phys_level0_sa.height == 1);
+   assert(surf->phys_level0_sa.height == fmtl->bh);
    assert(surf->phys_level0_sa.depth == 1);
    assert(surf->samples == 1);
 
diff --git a/src/intel/isl/isl_surface_state.c b/src/intel/isl/isl_surface_state.c
index 979e140..210308c 100644
--- a/src/intel/isl/isl_surface_state.c
+++ b/src/intel/isl/isl_surface_state.c
@@ -215,6 +215,15 @@ isl_genX(surf_fill_state_s)(const struct isl_device *dev, void *state,
       assert(isl_format_supports_rendering(dev->info, info->view->format));
    else if (info->view->usage & ISL_SURF_USAGE_TEXTURE_BIT)
       assert(isl_format_supports_sampling(dev->info, info->view->format));
+
+   /* From the Sky Lake PRM Vol. 2d, RENDER_SURFACE_STATE::SurfaceFormat
+    *
+    *    This field cannot be a compressed (BC*, DXT*, FXT*, ETC*, EAC*)
+    *    format if the Surface Type is SURFTYPE_1D
+    */
+   if (info->surf->dim == ISL_SURF_DIM_1D)
+      assert(!isl_format_is_compressed(info->view->format));
+
    s.SurfaceFormat = info->view->format;
 
 #if GEN_IS_HASWELL
-- 
2.5.0.400.gff86faf