[Mesa-dev] [PATCH v2 9/9] radeonsi: enable ARB_query_buffer_object (v2)
Marek Olšák
maraeo at gmail.com
Wed Sep 28 13:38:43 UTC 2016
For the series:
Reviewed-by: Marek Olšák <marek.olsak at amd.com>
Regarding patch 8, I only skimmed through it.
Marek
On Thu, Sep 22, 2016 at 2:28 PM, Nicolai Hähnle <nhaehnle at gmail.com> wrote:
> From: Nicolai Hähnle <nicolai.haehnle at amd.com>
>
> v2: enable only when compute is available
> ---
> docs/features.txt | 2 +-
> docs/relnotes/12.1.0.html | 1 +
> src/gallium/drivers/radeonsi/si_pipe.c | 21 ++++++++++++++-------
> 3 files changed, 16 insertions(+), 8 deletions(-)
>
> diff --git a/docs/features.txt b/docs/features.txt
> index cb62286..3146ae8 100644
> --- a/docs/features.txt
> +++ b/docs/features.txt
> @@ -194,21 +194,21 @@ GL 4.4, GLSL 4.40 -- all DONE: i965/gen8+
> GL_ARB_buffer_storage DONE (i965, nv50, nvc0, r600, radeonsi)
> GL_ARB_clear_texture DONE (i965, nv50, nvc0, r600, radeonsi)
> GL_ARB_enhanced_layouts DONE (i965)
> - compile-time constant expressions DONE
> - explicit byte offsets for blocks DONE
> - forced alignment within blocks DONE
> - specified vec4-slot component numbers DONE (i965)
> - specified transform/feedback layout DONE
> - input/output block locations DONE
> GL_ARB_multi_bind DONE (all drivers)
> - GL_ARB_query_buffer_object DONE (i965/hsw+, nvc0)
> + GL_ARB_query_buffer_object DONE (i965/hsw+, nvc0, radeonsi)
> GL_ARB_texture_mirror_clamp_to_edge DONE (i965, nv50, nvc0, r600, radeonsi, llvmpipe, softpipe, swr)
> GL_ARB_texture_stencil8 DONE (i965/hsw+, nv50, nvc0, r600, radeonsi, llvmpipe, softpipe, swr)
> GL_ARB_vertex_type_10f_11f_11f_rev DONE (i965, nv50, nvc0, r600, radeonsi, llvmpipe, softpipe, swr)
>
> GL 4.5, GLSL 4.50:
>
> GL_ARB_ES3_1_compatibility DONE (i965/hsw+, nvc0, radeonsi)
> GL_ARB_clip_control DONE (i965, nv50, nvc0, r600, radeonsi, llvmpipe, softpipe, swr)
> GL_ARB_conditional_render_inverted DONE (i965, nv50, nvc0, r600, radeonsi, llvmpipe, softpipe, swr)
> GL_ARB_cull_distance DONE (i965, nv50, nvc0, radeonsi, llvmpipe, softpipe, swr)
> diff --git a/docs/relnotes/12.1.0.html b/docs/relnotes/12.1.0.html
> index fb1d714..bcdc1da 100644
> --- a/docs/relnotes/12.1.0.html
> +++ b/docs/relnotes/12.1.0.html
> @@ -45,20 +45,21 @@ Note: some of the new features are only available with certain drivers.
>
> <ul>
> <li>OpenGL ES 3.1 on i965/hsw</li>
> <li>OpenGL ES 3.2 on i965/gen9+ (Skylake and later)</li>
> <li>GL_ARB_ES3_1_compatibility on i965</li>
> <li>GL_ARB_ES3_2_compatibility on i965/gen8+</li>
> <li>GL_ARB_clear_texture on r600, radeonsi</li>
> <li>GL_ARB_cull_distance on radeonsi</li>
> <li>GL_ARB_enhanced_layouts on i965</li>
> <li>GL_ARB_indirect_parameters on radeonsi</li>
> +<li>GL_ARB_query_buffer_object on radeonsi</li>
> <li>GL_ARB_shader_draw_parameters on radeonsi</li>
> <li>GL_ARB_shader_group_vote on nvc0</li>
> <li>GL_ARB_shader_viewport_layer_array on i965/gen6+</li>
> <li>GL_ARB_stencil_texturing on i965/hsw</li>
> <li>GL_ARB_texture_stencil8 on i965/hsw</li>
> <li>GL_EXT_window_rectangles on nv50, nvc0</li>
> <li>GL_KHR_blend_equation_advanced on i965</li>
> <li>GL_KHR_texture_compression_astc_sliced_3d on i965</li>
> <li>GL_OES_copy_image on nv50, nvc0, r600, radeonsi, softpipe, llvmpipe</li>
> <li>GL_OES_geometry_shader on i965/gen8+, nvc0, radeonsi</li>
> diff --git a/src/gallium/drivers/radeonsi/si_pipe.c b/src/gallium/drivers/radeonsi/si_pipe.c
> index 730be9d..60ef548 100644
> --- a/src/gallium/drivers/radeonsi/si_pipe.c
> +++ b/src/gallium/drivers/radeonsi/si_pipe.c
> @@ -309,20 +309,30 @@ static struct pipe_context *si_create_context(struct pipe_screen *screen,
> return &sctx->b.b;
> fail:
> fprintf(stderr, "radeonsi: Failed to create a context.\n");
> si_destroy_context(&sctx->b.b);
> return NULL;
> }
>
> /*
> * pipe_screen
> */
> +static bool si_have_tgsi_compute(struct si_screen *sscreen)
> +{
> + /* Old kernels disallowed some register writes for SI
> + * that are used for indirect dispatches. */
> + return HAVE_LLVM >= 0x309 &&
> + (sscreen->b.chip_class >= CIK ||
> + sscreen->b.info.drm_major == 3 ||
> + (sscreen->b.info.drm_major == 2 &&
> + sscreen->b.info.drm_minor >= 45));
> +}
>
> static int si_get_param(struct pipe_screen* pscreen, enum pipe_cap param)
> {
> struct si_screen *sscreen = (struct si_screen *)pscreen;
>
> switch (param) {
> /* Supported features (boolean caps). */
> case PIPE_CAP_TWO_SIDED_STENCIL:
> case PIPE_CAP_MAX_DUAL_SOURCE_RENDER_TARGETS:
> case PIPE_CAP_ANISOTROPIC_FILTER:
> @@ -441,26 +451,28 @@ static int si_get_param(struct pipe_screen* pscreen, enum pipe_cap param)
> case PIPE_CAP_BUFFER_SAMPLER_VIEW_RGBA_ONLY:
> return 0;
>
> /* Unsupported features. */
> case PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT:
> case PIPE_CAP_TGSI_CAN_COMPACT_CONSTANTS:
> case PIPE_CAP_USER_VERTEX_BUFFERS:
> case PIPE_CAP_FAKE_SW_MSAA:
> case PIPE_CAP_TEXTURE_GATHER_OFFSETS:
> case PIPE_CAP_VERTEXID_NOBASE:
> - case PIPE_CAP_QUERY_BUFFER_OBJECT:
> case PIPE_CAP_PRIMITIVE_RESTART_FOR_PATCHES:
> case PIPE_CAP_TGSI_VOTE:
> case PIPE_CAP_MAX_WINDOW_RECTANGLES:
> return 0;
>
> + case PIPE_CAP_QUERY_BUFFER_OBJECT:
> + return si_have_tgsi_compute(sscreen);
> +
> case PIPE_CAP_DRAW_PARAMETERS:
> case PIPE_CAP_MULTI_DRAW_INDIRECT:
> case PIPE_CAP_MULTI_DRAW_INDIRECT_PARAMS:
> return sscreen->has_draw_indirect_multi;
>
> case PIPE_CAP_MAX_SHADER_PATCH_VARYINGS:
> return 30;
>
> case PIPE_CAP_TEXTURE_BORDER_COLOR_QUIRK:
> return PIPE_QUIRK_TEXTURE_BORDER_COLOR_SWIZZLE_R600;
> @@ -560,26 +572,21 @@ static int si_get_shader_param(struct pipe_screen* pscreen, unsigned shader, enu
> return 0;
> break;
> case PIPE_SHADER_COMPUTE:
> switch (param) {
> case PIPE_SHADER_CAP_PREFERRED_IR:
> return PIPE_SHADER_IR_NATIVE;
>
> case PIPE_SHADER_CAP_SUPPORTED_IRS: {
> int ir = 1 << PIPE_SHADER_IR_NATIVE;
>
> - /* Old kernels disallowed some register writes for SI
> - * that are used for indirect dispatches. */
> - if (HAVE_LLVM >= 0x309 && (sscreen->b.chip_class >= CIK ||
> - sscreen->b.info.drm_major == 3 ||
> - (sscreen->b.info.drm_major == 2 &&
> - sscreen->b.info.drm_minor >= 45)))
> + if (si_have_tgsi_compute(sscreen))
> ir |= 1 << PIPE_SHADER_IR_TGSI;
>
> return ir;
> }
> case PIPE_SHADER_CAP_DOUBLES:
> return HAVE_LLVM >= 0x0307;
>
> case PIPE_SHADER_CAP_MAX_CONST_BUFFER_SIZE: {
> uint64_t max_const_buffer_size;
> pscreen->get_compute_param(pscreen, PIPE_SHADER_IR_TGSI,
> --
> 2.7.4
>
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