[Mesa-dev] [PATCH] radeonsi: fix broken texture filtering on SIK-CIK since GFX9 changes

[Nicolai Hähnle]

On 03.04.2017 02:01, Marek Olšák wrote:
> From: Marek Olšák <marek.olsak at amd.com>
>
> Don't clear state[7] on SI-CIK, and only do the meta stuff on VI+.
>
> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=100531

Makes sense. Please add

Fixes: 5abf60076ce4 ("radeonsi/gfx9: image descriptor changes in mutable 
fields")

Reviewed-by: Nicolai Hähnle <nicolai.haehnle at amd.com>

> ---
>  src/gallium/drivers/radeonsi/si_descriptors.c | 32 ++++++++++++++-------------
>  1 file changed, 17 insertions(+), 15 deletions(-)
>
> diff --git a/src/gallium/drivers/radeonsi/si_descriptors.c b/src/gallium/drivers/radeonsi/si_descriptors.c
> index 2b91158..8f5a16b 100644
> --- a/src/gallium/drivers/radeonsi/si_descriptors.c
> +++ b/src/gallium/drivers/radeonsi/si_descriptors.c
> @@ -397,40 +397,42 @@ void si_set_mutable_tex_desc_fields(struct si_screen *sscreen,
>  	if (sscreen->b.chip_class >= GFX9) {
>  		/* Only stencil_offset needs to be added here. */
>  		if (is_stencil)
>  			va += tex->surface.u.gfx9.stencil_offset;
>  		else
>  			va += tex->surface.u.gfx9.surf_offset;
>  	} else {
>  		va += base_level_info->offset;
>  	}
>
> -	if (vi_dcc_enabled(tex, first_level)) {
> -		meta_va = (!tex->dcc_separate_buffer ? tex->resource.gpu_address : 0) +
> -			  tex->dcc_offset;
> -
> -		if (sscreen->b.chip_class <= VI)
> -			meta_va += base_level_info->dcc_offset;
> -	} else if (tex->tc_compatible_htile && !is_stencil) {
> -		meta_va = tex->htile_buffer->gpu_address;
> -	}
> -
>  	state[0] = va >> 8;
>  	state[1] &= C_008F14_BASE_ADDRESS_HI;
>  	state[1] |= S_008F14_BASE_ADDRESS_HI(va >> 40);
>
> -	state[6] &= C_008F28_COMPRESSION_EN;
> -	state[7] = 0;
> +	if (sscreen->b.chip_class >= VI) {
> +		state[6] &= C_008F28_COMPRESSION_EN;
> +		state[7] = 0;
>
> -	if (meta_va) {
> -		state[6] |= S_008F28_COMPRESSION_EN(1);
> -		state[7] = meta_va >> 8;
> +		if (vi_dcc_enabled(tex, first_level)) {
> +			meta_va = (!tex->dcc_separate_buffer ? tex->resource.gpu_address : 0) +
> +				  tex->dcc_offset;
> +
> +			if (sscreen->b.chip_class <= VI)
> +				meta_va += base_level_info->dcc_offset;
> +		} else if (tex->tc_compatible_htile && !is_stencil) {
> +			meta_va = tex->htile_buffer->gpu_address;
> +		}
> +
> +		if (meta_va) {
> +			state[6] |= S_008F28_COMPRESSION_EN(1);
> +			state[7] = meta_va >> 8;
> +		}
>  	}
>
>  	if (sscreen->b.chip_class >= GFX9) {
>  		state[3] &= C_008F1C_SW_MODE;
>  		state[4] &= C_008F20_PITCH_GFX9;
>
>  		if (is_stencil) {
>  			state[3] |= S_008F1C_SW_MODE(tex->surface.u.gfx9.stencil.swizzle_mode);
>  			state[4] |= S_008F20_PITCH_GFX9(tex->surface.u.gfx9.stencil.epitch);
>  		} else {
>


-- 
Lerne, wie die Welt wirklich ist,
Aber vergiss niemals, wie sie sein sollte.