[Mesa-dev] [PATCH 1/4] anv/blorp: Align vertex buffers to 64B

[Kenneth Graunke]

On Friday, March 31, 2017 4:17:08 PM PDT Jason Ekstrand wrote:
> This fixes issues seen when adding support for full 48-bit addresses.
> The 48-bit addresses themselves have nothing to do with it other than
> that it caused the kernel to place buffers slightly differently so they
> interacted differently with the caches.
> 
> Cc: "13.0 17.0" <mesa-stable at lists.freedesktop.org>
> ---
>  src/intel/vulkan/genX_blorp_exec.c | 14 +++++++++++++-
>  1 file changed, 13 insertions(+), 1 deletion(-)
> 
> diff --git a/src/intel/vulkan/genX_blorp_exec.c b/src/intel/vulkan/genX_blorp_exec.c
> index 1d07fd7..402f6d2 100644
> --- a/src/intel/vulkan/genX_blorp_exec.c
> +++ b/src/intel/vulkan/genX_blorp_exec.c
> @@ -115,8 +115,20 @@ blorp_alloc_vertex_buffer(struct blorp_batch *batch, uint32_t size,
>                            struct blorp_address *addr)
>  {
>     struct anv_cmd_buffer *cmd_buffer = batch->driver_batch;
> +
> +   /* From the Sky Lake PRM, 3DSTATE_VERTEX_BUFFERS:

Skylake PRM.  Might be worth mentioning that this workaround is needed
starting with Broadwell (according to the internal docs), though it
doesn't seem to be in the PRMs until Skylake.

> +    *
> +    *    "The VF cache needs to be invalidated before binding and then using
> +    *    Vertex Buffers that overlap with any previously bound Vertex Buffer
> +    *    (at a 64B granularity) since the last invalidation.  A VF cache
> +    *    invalidate is performed by setting the "VF Cache Invalidation Enable"
> +    *    bit in PIPE_CONTROL."
> +    *
> +    * In order to avoid this problem, we align all vertex buffer allocations
> +    * to 64 bytes.

I see, because we're streaming out vertex data in the dynamic state
buffer, if we align it, it will never overlap at a 64B granularity.
Nice and simple fix.

Patches 1-2 are:
Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>
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