[Mesa-dev] [PATCH 3/9] nvc0/ir: Emit OP_SHFL
Boyan Ding
boyan.j.ding at gmail.com
Sat Apr 8 09:51:15 UTC 2017
---
.../drivers/nouveau/codegen/nv50_ir_emit_nvc0.cpp | 51 ++++++++++++++++++++++
1 file changed, 51 insertions(+)
diff --git a/src/gallium/drivers/nouveau/codegen/nv50_ir_emit_nvc0.cpp b/src/gallium/drivers/nouveau/codegen/nv50_ir_emit_nvc0.cpp
index d5a310f88c..8dd73bd77d 100644
--- a/src/gallium/drivers/nouveau/codegen/nv50_ir_emit_nvc0.cpp
+++ b/src/gallium/drivers/nouveau/codegen/nv50_ir_emit_nvc0.cpp
@@ -150,6 +150,8 @@ private:
void emitPIXLD(const Instruction *);
+ void emitSHFL(const Instruction *);
+
void emitVOTE(const Instruction *);
inline void defId(const ValueDef&, const int pos);
@@ -2529,6 +2531,52 @@ CodeEmitterNVC0::emitPIXLD(const Instruction *i)
}
void
+CodeEmitterNVC0::emitSHFL(const Instruction *i)
+{
+ code[0] = 0x00000005;
+ code[1] = 0x88000000 | (i->subOp << 23);
+
+ emitPredicate(i);
+
+ defId(i->def(0), 14);
+ srcId(i->src(0), 20);
+
+ switch (i->src(1).getFile()) {
+ case FILE_GPR:
+ srcId(i->src(1), 26);
+ break;
+ case FILE_IMMEDIATE:
+ code[0] |= (i->src(1).get()->asImm()->reg.data.u32 & 0x1f) << 26;
+ code[0] |= 1 << 5;
+ break;
+ default:
+ assert(!"invalid src1 file");
+ break;
+ }
+
+ switch (i->src(2).getFile()) {
+ case FILE_GPR:
+ srcId(i->src(2), 49);
+ break;
+ case FILE_IMMEDIATE:
+ code[1] |= (i->src(2).get()->asImm()->reg.data.u32 & 0x1fff) << 10;
+ code[0] |= 1 << 6;
+ break;
+ default:
+ assert(!"invalid src2 file");
+ break;
+ }
+
+ if (!i->defExists(1)) {
+ code[0] |= 3 << 8;
+ code[1] |= 1 << 26;
+ } else {
+ assert(i->def(1).getFile() == FILE_PREDICATE);
+ setPDSTL(i->def(1));
+ }
+}
+
+void
CodeEmitterNVC0::emitVOTE(const Instruction *i)
{
assert(i->src(0).getFile() == FILE_PREDICATE);
@@ -2837,6 +2885,9 @@ CodeEmitterNVC0::emitInstruction(Instruction *insn)
case OP_PIXLD:
emitPIXLD(insn);
break;
+ case OP_SHFL:
+ emitSHFL(insn);
+ break;
case OP_VOTE:
emitVOTE(insn);
break;
--
2.12.1
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