[Mesa-dev] [PATCH 1/2] i965/vec4: set swizzle when loading an uniform

[Francisco Jerez]

Samuel Iglesias Gonsálvez <siglesias at igalia.com> writes:

> It was setting XYWZ swizzle to all uniforms, no matter if they were
> a vector or not.
>
> Signed-off-by: Samuel Iglesias Gonsálvez <siglesias at igalia.com>
> Cc: currojerez at riseup.net

Don't you need to CC mesa-stable here and in the next patch?

> ---
>  src/intel/compiler/brw_vec4_nir.cpp | 1 +
>  1 file changed, 1 insertion(+)
>
> diff --git a/src/intel/compiler/brw_vec4_nir.cpp b/src/intel/compiler/brw_vec4_nir.cpp
> index a82d52088a8..5f4488c7e86 100644
> --- a/src/intel/compiler/brw_vec4_nir.cpp
> +++ b/src/intel/compiler/brw_vec4_nir.cpp
> @@ -863,6 +863,7 @@ vec4_visitor::nir_emit_intrinsic(nir_intrinsic_instr *instr)
>           unsigned offset = const_offset->u32[0] + shift * 4;
>           src.offset = ROUND_DOWN_TO(offset, 16);
>           shift = (offset % 16) / 4;
> +         src.swizzle = brw_swizzle_for_size(instr->num_components);

What about the indirect case a few lines below?  Isn't the swizzle passed
to the mov indirect instruction still bogus?

>           src.swizzle += BRW_SWIZZLE4(shift, shift, shift, shift);
>  
>           emit(MOV(dest, src));
> -- 
> 2.11.0
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