[Mesa-dev] [PATCH 07/61] radeonsi: adjust ESGS ring buffer size computation on VI

[Marek Olšák]

From: Marek Olšák <marek.olsak at amd.com>

Cc: 17.0 17.1 <mesa-stable at lists.freedesktop.org>
---
 src/gallium/drivers/radeonsi/si_state_shaders.c | 5 ++++-
 1 file changed, 4 insertions(+), 1 deletion(-)

diff --git a/src/gallium/drivers/radeonsi/si_state_shaders.c b/src/gallium/drivers/radeonsi/si_state_shaders.c
index 34cd6d4..3a604eb 100644
--- a/src/gallium/drivers/radeonsi/si_state_shaders.c
+++ b/src/gallium/drivers/radeonsi/si_state_shaders.c
@@ -2108,21 +2108,24 @@ static bool si_update_gs_ring_buffers(struct si_context *sctx)
 {
 	struct si_shader_selector *es =
 		sctx->tes_shader.cso ? sctx->tes_shader.cso : sctx->vs_shader.cso;
 	struct si_shader_selector *gs = sctx->gs_shader.cso;
 	struct si_pm4_state *pm4;
 
 	/* Chip constants. */
 	unsigned num_se = sctx->screen->b.info.max_se;
 	unsigned wave_size = 64;
 	unsigned max_gs_waves = 32 * num_se; /* max 32 per SE on GCN */
-	unsigned gs_vertex_reuse = 16 * num_se; /* GS_VERTEX_REUSE register (per SE) */
+	/* On SI-CI, the value comes from VGT_GS_VERTEX_REUSE = 16.
+	 * On VI+, the value comes from VGT_VERTEX_REUSE_BLOCK_CNTL = 30 (+2).
+	 */
+	unsigned gs_vertex_reuse = (sctx->b.chip_class >= VI ? 32 : 16) * num_se;
 	unsigned alignment = 256 * num_se;
 	/* The maximum size is 63.999 MB per SE. */
 	unsigned max_size = ((unsigned)(63.999 * 1024 * 1024) & ~255) * num_se;
 
 	/* Calculate the minimum size. */
 	unsigned min_esgs_ring_size = align(es->esgs_itemsize * gs_vertex_reuse *
 					    wave_size, alignment);
 
 	/* These are recommended sizes, not minimum sizes. */
 	unsigned esgs_ring_size = max_gs_waves * 2 * wave_size *
-- 
2.7.4