[Mesa-dev] [PATCH 35/61] radeonsi/gfx9: add GS user SGPRs

Marek Olšák maraeo at gmail.com
Mon Apr 24 08:45:32 UTC 2017


From: Marek Olšák <marek.olsak at amd.com>

---
 src/gallium/drivers/radeonsi/si_descriptors.c   | 15 +++++++++++----
 src/gallium/drivers/radeonsi/si_shader.c        |  2 +-
 src/gallium/drivers/radeonsi/si_shader.h        | 13 ++++++++++++-
 src/gallium/drivers/radeonsi/si_state_shaders.c |  2 +-
 4 files changed, 25 insertions(+), 7 deletions(-)

diff --git a/src/gallium/drivers/radeonsi/si_descriptors.c b/src/gallium/drivers/radeonsi/si_descriptors.c
index 5b7298e..fc94e43 100644
--- a/src/gallium/drivers/radeonsi/si_descriptors.c
+++ b/src/gallium/drivers/radeonsi/si_descriptors.c
@@ -1985,59 +1985,66 @@ void si_emit_compute_shader_userdata(struct si_context *sctx)
 }
 
 /* INIT/DEINIT/UPLOAD */
 
 void si_init_all_descriptors(struct si_context *sctx)
 {
 	int i;
 	unsigned ce_offset = 0;
 
 	STATIC_ASSERT(GFX9_SGPR_TCS_CONST_BUFFERS % 2 == 0);
+	STATIC_ASSERT(GFX9_SGPR_GS_CONST_BUFFERS % 2 == 0);
 
 	for (i = 0; i < SI_NUM_SHADERS; i++) {
 		bool gfx9_tcs = sctx->b.chip_class == GFX9 &&
 				i == PIPE_SHADER_TESS_CTRL;
+		bool gfx9_gs = sctx->b.chip_class == GFX9 &&
+			       i == PIPE_SHADER_GEOMETRY;
 		/* GFX9 has only 4KB of CE, while previous chips had 32KB.
 		 * Rarely used descriptors don't use CE RAM.
 		 */
 		bool big_ce = sctx->b.chip_class <= VI;
 		bool images_use_ce = big_ce;
 		bool shaderbufs_use_ce = big_ce ||
 					 i == PIPE_SHADER_COMPUTE;
 		bool samplers_use_ce = big_ce ||
 				       i == PIPE_SHADER_FRAGMENT;
 
 		si_init_buffer_resources(&sctx->const_buffers[i],
 					 si_const_buffer_descriptors(sctx, i),
 					 SI_NUM_CONST_BUFFERS,
 					 gfx9_tcs ? GFX9_SGPR_TCS_CONST_BUFFERS :
-						    SI_SGPR_CONST_BUFFERS,
+					 gfx9_gs ? GFX9_SGPR_GS_CONST_BUFFERS :
+						   SI_SGPR_CONST_BUFFERS,
 					 RADEON_USAGE_READ, RADEON_PRIO_CONST_BUFFER,
 					 &ce_offset);
 		si_init_buffer_resources(&sctx->shader_buffers[i],
 					 si_shader_buffer_descriptors(sctx, i),
 					 SI_NUM_SHADER_BUFFERS,
 					 gfx9_tcs ? GFX9_SGPR_TCS_SHADER_BUFFERS :
-						    SI_SGPR_SHADER_BUFFERS,
+					 gfx9_gs ? GFX9_SGPR_GS_SHADER_BUFFERS :
+						   SI_SGPR_SHADER_BUFFERS,
 					 RADEON_USAGE_READWRITE, RADEON_PRIO_SHADER_RW_BUFFER,
 					 shaderbufs_use_ce ? &ce_offset : NULL);
 
 		si_init_descriptors(si_sampler_descriptors(sctx, i),
 				    gfx9_tcs ? GFX9_SGPR_TCS_SAMPLERS :
-					       SI_SGPR_SAMPLERS,
+				    gfx9_gs ? GFX9_SGPR_GS_SAMPLERS :
+					      SI_SGPR_SAMPLERS,
 				    16, SI_NUM_SAMPLERS,
 				    null_texture_descriptor,
 				    samplers_use_ce ? &ce_offset : NULL);
 
 		si_init_descriptors(si_image_descriptors(sctx, i),
 				    gfx9_tcs ? GFX9_SGPR_TCS_IMAGES :
-					       SI_SGPR_IMAGES,
+				    gfx9_gs ? GFX9_SGPR_GS_IMAGES :
+					      SI_SGPR_IMAGES,
 				    8, SI_NUM_IMAGES,
 				    null_image_descriptor,
 				    images_use_ce ? &ce_offset : NULL);
 	}
 
 	si_init_buffer_resources(&sctx->rw_buffers,
 				 &sctx->descriptors[SI_DESCS_RW_BUFFERS],
 				 SI_NUM_RW_BUFFERS, SI_SGPR_RW_BUFFERS,
 				 RADEON_USAGE_READWRITE, RADEON_PRIO_SHADER_RINGS,
 				 &ce_offset);
diff --git a/src/gallium/drivers/radeonsi/si_shader.c b/src/gallium/drivers/radeonsi/si_shader.c
index 752f819..ee8cae1 100644
--- a/src/gallium/drivers/radeonsi/si_shader.c
+++ b/src/gallium/drivers/radeonsi/si_shader.c
@@ -7526,21 +7526,21 @@ static void si_get_ps_epilog_key(struct si_shader *shader,
 	key->ps_epilog.states = shader->key.part.ps.epilog;
 }
 
 /**
  * Build the GS prolog function. Rotate the input vertices for triangle strips
  * with adjacency.
  */
 static void si_build_gs_prolog_function(struct si_shader_context *ctx,
 					union si_shader_part_key *key)
 {
-	const unsigned num_sgprs = SI_GS_NUM_USER_SGPR + 2;
+	const unsigned num_sgprs = GFX6_GS_NUM_USER_SGPR + 2;
 	const unsigned num_vgprs = 8;
 	struct gallivm_state *gallivm = &ctx->gallivm;
 	LLVMBuilderRef builder = gallivm->builder;
 	LLVMTypeRef params[32];
 	LLVMTypeRef returns[32];
 	LLVMValueRef func, ret;
 
 	for (unsigned i = 0; i < num_sgprs; ++i) {
 		params[i] = ctx->i32;
 		returns[i] = ctx->i32;
diff --git a/src/gallium/drivers/radeonsi/si_shader.h b/src/gallium/drivers/radeonsi/si_shader.h
index 76f7743..75df99d 100644
--- a/src/gallium/drivers/radeonsi/si_shader.h
+++ b/src/gallium/drivers/radeonsi/si_shader.h
@@ -123,22 +123,33 @@ enum {
 	GFX9_SGPR_TCS_CONST_BUFFERS,
 	GFX9_SGPR_TCS_CONST_BUFFERS_HI,
 	GFX9_SGPR_TCS_SAMPLERS,  /* images & sampler states interleaved */
 	GFX9_SGPR_TCS_SAMPLERS_HI,
 	GFX9_SGPR_TCS_IMAGES,
 	GFX9_SGPR_TCS_IMAGES_HI,
 	GFX9_SGPR_TCS_SHADER_BUFFERS,
 	GFX9_SGPR_TCS_SHADER_BUFFERS_HI,
 	GFX9_TCS_NUM_USER_SGPR,
 
+	/* GFX9: Merged ES-GS (VS-GS or TES-GS). */
+	GFX9_SGPR_GS_CONST_BUFFERS = SI_VS_NUM_USER_SGPR,
+	GFX9_SGPR_GS_CONST_BUFFERS_HI,
+	GFX9_SGPR_GS_SAMPLERS,
+	GFX9_SGPR_GS_SAMPLERS_HI,
+	GFX9_SGPR_GS_IMAGES,
+	GFX9_SGPR_GS_IMAGES_HI,
+	GFX9_SGPR_GS_SHADER_BUFFERS,
+	GFX9_SGPR_GS_SHADER_BUFFERS_HI,
+	GFX9_GS_NUM_USER_SGPR,
+
 	/* GS limits */
-	SI_GS_NUM_USER_SGPR = SI_NUM_RESOURCE_SGPRS,
+	GFX6_GS_NUM_USER_SGPR = SI_NUM_RESOURCE_SGPRS,
 	SI_GSCOPY_NUM_USER_SGPR = SI_SGPR_RW_BUFFERS_HI + 1,
 
 	/* PS only */
 	SI_SGPR_ALPHA_REF	= SI_NUM_RESOURCE_SGPRS,
 	SI_PS_NUM_USER_SGPR,
 
 	/* CS only */
 	SI_SGPR_GRID_SIZE = SI_NUM_RESOURCE_SGPRS,
 	SI_SGPR_BLOCK_SIZE = SI_SGPR_GRID_SIZE + 3,
 	SI_CS_NUM_USER_SGPR = SI_SGPR_BLOCK_SIZE + 3
diff --git a/src/gallium/drivers/radeonsi/si_state_shaders.c b/src/gallium/drivers/radeonsi/si_state_shaders.c
index a330bc0..806d55b 100644
--- a/src/gallium/drivers/radeonsi/si_state_shaders.c
+++ b/src/gallium/drivers/radeonsi/si_state_shaders.c
@@ -636,21 +636,21 @@ static void si_shader_gs(struct si_shader *shader)
 	si_pm4_add_bo(pm4, shader->bo, RADEON_USAGE_READ, RADEON_PRIO_SHADER_BINARY);
 	si_pm4_set_reg(pm4, R_00B220_SPI_SHADER_PGM_LO_GS, va >> 8);
 	si_pm4_set_reg(pm4, R_00B224_SPI_SHADER_PGM_HI_GS, va >> 40);
 
 	si_pm4_set_reg(pm4, R_00B228_SPI_SHADER_PGM_RSRC1_GS,
 		       S_00B228_VGPRS((shader->config.num_vgprs - 1) / 4) |
 		       S_00B228_SGPRS((shader->config.num_sgprs - 1) / 8) |
 		       S_00B228_DX10_CLAMP(1) |
 		       S_00B228_FLOAT_MODE(shader->config.float_mode));
 	si_pm4_set_reg(pm4, R_00B22C_SPI_SHADER_PGM_RSRC2_GS,
-		       S_00B22C_USER_SGPR(SI_GS_NUM_USER_SGPR) |
+		       S_00B22C_USER_SGPR(GFX6_GS_NUM_USER_SGPR) |
 		       S_00B22C_SCRATCH_EN(shader->config.scratch_bytes_per_wave > 0));
 }
 
 /**
  * Compute the state for \p shader, which will run as a vertex shader on the
  * hardware.
  *
  * If \p gs is non-NULL, it points to the geometry shader for which this shader
  * is the copy shader.
  */
-- 
2.7.4



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