[Mesa-dev] [PATCH 58/61] radeonsi: use si_insert_input_ret in si_llvm_emit_tcs_epilogue

[Marek Olšák]

From: Marek Olšák <marek.olsak at amd.com>

---
 src/gallium/drivers/radeonsi/si_shader.c | 29 ++++++++++-------------------
 1 file changed, 10 insertions(+), 19 deletions(-)

diff --git a/src/gallium/drivers/radeonsi/si_shader.c b/src/gallium/drivers/radeonsi/si_shader.c
index 13cbd0a..974be02 100644
--- a/src/gallium/drivers/radeonsi/si_shader.c
+++ b/src/gallium/drivers/radeonsi/si_shader.c
@@ -2672,59 +2672,50 @@ si_insert_input_ptr_as_2xi32(struct si_shader_context *ctx, LLVMValueRef ret,
 	hi = LLVMBuildExtractElement(builder, ptr, ctx->i32_1, "");
 	ret = LLVMBuildInsertValue(builder, ret, lo, return_index, "");
 	return LLVMBuildInsertValue(builder, ret, hi, return_index + 1, "");
 }
 
 /* This only writes the tessellation factor levels. */
 static void si_llvm_emit_tcs_epilogue(struct lp_build_tgsi_context *bld_base)
 {
 	struct si_shader_context *ctx = si_shader_context(bld_base);
 	LLVMValueRef rel_patch_id, invocation_id, tf_lds_offset;
-	LLVMValueRef offchip_soffset, offchip_layout;
 
 	si_copy_tcs_inputs(bld_base);
 
 	rel_patch_id = get_rel_patch_id(ctx);
 	invocation_id = unpack_param(ctx, ctx->param_tcs_rel_ids, 8, 5);
 	tf_lds_offset = get_tcs_out_current_patch_data_offset(ctx);
 
 	/* Return epilog parameters from this function. */
 	LLVMBuilderRef builder = ctx->gallivm.builder;
 	LLVMValueRef ret = ctx->return_value;
-	LLVMValueRef tf_soffset;
 	unsigned vgpr;
 
-	offchip_layout = LLVMGetParam(ctx->main_fn,
-				      ctx->param_tcs_offchip_layout);
-	offchip_soffset = LLVMGetParam(ctx->main_fn,
-				       ctx->param_tcs_offchip_offset);
-	tf_soffset = LLVMGetParam(ctx->main_fn,
-				  ctx->param_tcs_factor_offset);
-
 	ret = si_insert_input_ptr_as_2xi32(ctx, ret,
 					   ctx->param_rw_buffers, 0);
 
 	if (ctx->screen->b.chip_class >= GFX9) {
-		ret = LLVMBuildInsertValue(builder, ret, offchip_layout,
-					   8 + GFX9_SGPR_TCS_OFFCHIP_LAYOUT, "");
+		ret = si_insert_input_ret(ctx, ret, ctx->param_tcs_offchip_layout,
+					  8 + GFX9_SGPR_TCS_OFFCHIP_LAYOUT);
 		/* Tess offchip and tess factor offsets are at the beginning. */
-		ret = LLVMBuildInsertValue(builder, ret, offchip_soffset, 2, "");
-		ret = LLVMBuildInsertValue(builder, ret, tf_soffset, 4, "");
+		ret = si_insert_input_ret(ctx, ret, ctx->param_tcs_offchip_offset, 2);
+		ret = si_insert_input_ret(ctx, ret, ctx->param_tcs_factor_offset, 4);
 		vgpr = 8 + GFX9_SGPR_TCS_OFFCHIP_LAYOUT + 1;
 	} else {
-		ret = LLVMBuildInsertValue(builder, ret, offchip_layout,
-					   GFX6_SGPR_TCS_OFFCHIP_LAYOUT, "");
+		ret = si_insert_input_ret(ctx, ret, ctx->param_tcs_offchip_layout,
+					  GFX6_SGPR_TCS_OFFCHIP_LAYOUT);
 		/* Tess offchip and tess factor offsets are after user SGPRs. */
-		ret = LLVMBuildInsertValue(builder, ret, offchip_soffset,
-					   GFX6_TCS_NUM_USER_SGPR, "");
-		ret = LLVMBuildInsertValue(builder, ret, tf_soffset,
-					   GFX6_TCS_NUM_USER_SGPR + 1, "");
+		ret = si_insert_input_ret(ctx, ret, ctx->param_tcs_offchip_offset,
+					  GFX6_TCS_NUM_USER_SGPR);
+		ret = si_insert_input_ret(ctx, ret, ctx->param_tcs_factor_offset,
+					  GFX6_TCS_NUM_USER_SGPR + 1);
 		vgpr = GFX6_TCS_NUM_USER_SGPR + 2;
 	}
 
 	/* VGPRs */
 	rel_patch_id = bitcast(bld_base, TGSI_TYPE_FLOAT, rel_patch_id);
 	invocation_id = bitcast(bld_base, TGSI_TYPE_FLOAT, invocation_id);
 	tf_lds_offset = bitcast(bld_base, TGSI_TYPE_FLOAT, tf_lds_offset);
 
 	ret = LLVMBuildInsertValue(builder, ret, rel_patch_id, vgpr++, "");
 	ret = LLVMBuildInsertValue(builder, ret, invocation_id, vgpr++, "");
-- 
2.7.4