[Mesa-dev] [PATCH 1/2] radeonsi: add a HUD query for draw calls with primitive restart

Samuel Pitoiset samuel.pitoiset at gmail.com
Mon Apr 24 19:11:26 UTC 2017


Reviewed-by: Samuel Pitoiset <samuel.pitoiset at gmail.com>

On 04/24/2017 03:22 PM, Marek Olšák wrote:
> From: Marek Olšák <marek.olsak at amd.com>
> 
> ---
>   src/gallium/drivers/radeon/r600_pipe_common.h | 1 +
>   src/gallium/drivers/radeon/r600_query.c       | 7 +++++++
>   src/gallium/drivers/radeon/r600_query.h       | 1 +
>   src/gallium/drivers/radeonsi/si_state_draw.c  | 2 ++
>   4 files changed, 11 insertions(+)
> 
> diff --git a/src/gallium/drivers/radeon/r600_pipe_common.h b/src/gallium/drivers/radeon/r600_pipe_common.h
> index fbd0ac7..3e83d37 100644
> --- a/src/gallium/drivers/radeon/r600_pipe_common.h
> +++ b/src/gallium/drivers/radeon/r600_pipe_common.h
> @@ -573,20 +573,21 @@ struct r600_common_context {
>   	unsigned flags; /* flush flags */
>   
>   	/* Queries. */
>   	/* Maintain the list of active queries for pausing between IBs. */
>   	int				num_occlusion_queries;
>   	int				num_perfect_occlusion_queries;
>   	struct list_head		active_queries;
>   	unsigned			num_cs_dw_queries_suspend;
>   	/* Misc stats. */
>   	unsigned			num_draw_calls;
> +	unsigned			num_prim_restart_calls;
>   	unsigned			num_spill_draw_calls;
>   	unsigned			num_compute_calls;
>   	unsigned			num_spill_compute_calls;
>   	unsigned			num_dma_calls;
>   	unsigned			num_cp_dma_calls;
>   	unsigned			num_vs_flushes;
>   	unsigned			num_ps_flushes;
>   	unsigned			num_cs_flushes;
>   	unsigned			num_fb_cache_flushes;
>   	unsigned			num_L2_invalidates;
> diff --git a/src/gallium/drivers/radeon/r600_query.c b/src/gallium/drivers/radeon/r600_query.c
> index 0980eca..cbf4bba 100644
> --- a/src/gallium/drivers/radeon/r600_query.c
> +++ b/src/gallium/drivers/radeon/r600_query.c
> @@ -90,20 +90,23 @@ static bool r600_query_sw_begin(struct r600_common_context *rctx,
>   	struct r600_query_sw *query = (struct r600_query_sw *)rquery;
>   	enum radeon_value_id ws_id;
>   
>   	switch(query->b.type) {
>   	case PIPE_QUERY_TIMESTAMP_DISJOINT:
>   	case PIPE_QUERY_GPU_FINISHED:
>   		break;
>   	case R600_QUERY_DRAW_CALLS:
>   		query->begin_result = rctx->num_draw_calls;
>   		break;
> +	case R600_QUERY_PRIM_RESTART_CALLS:
> +		query->begin_result = rctx->num_prim_restart_calls;
> +		break;
>   	case R600_QUERY_SPILL_DRAW_CALLS:
>   		query->begin_result = rctx->num_spill_draw_calls;
>   		break;
>   	case R600_QUERY_COMPUTE_CALLS:
>   		query->begin_result = rctx->num_compute_calls;
>   		break;
>   	case R600_QUERY_SPILL_COMPUTE_CALLS:
>   		query->begin_result = rctx->num_spill_compute_calls;
>   		break;
>   	case R600_QUERY_DMA_CALLS:
> @@ -214,20 +217,23 @@ static bool r600_query_sw_end(struct r600_common_context *rctx,
>   
>   	switch(query->b.type) {
>   	case PIPE_QUERY_TIMESTAMP_DISJOINT:
>   		break;
>   	case PIPE_QUERY_GPU_FINISHED:
>   		rctx->b.flush(&rctx->b, &query->fence, PIPE_FLUSH_DEFERRED);
>   		break;
>   	case R600_QUERY_DRAW_CALLS:
>   		query->end_result = rctx->num_draw_calls;
>   		break;
> +	case R600_QUERY_PRIM_RESTART_CALLS:
> +		query->end_result = rctx->num_prim_restart_calls;
> +		break;
>   	case R600_QUERY_SPILL_DRAW_CALLS:
>   		query->end_result = rctx->num_spill_draw_calls;
>   		break;
>   	case R600_QUERY_COMPUTE_CALLS:
>   		query->end_result = rctx->num_compute_calls;
>   		break;
>   	case R600_QUERY_SPILL_COMPUTE_CALLS:
>   		query->end_result = rctx->num_spill_compute_calls;
>   		break;
>   	case R600_QUERY_DMA_CALLS:
> @@ -1754,20 +1760,21 @@ void r600_query_fix_enabled_rb_mask(struct r600_common_screen *rscreen)
>   	XFULL(name_, query_type_, type_, result_type_, ~(unsigned)0)
>   
>   #define XG(group_, name_, query_type_, type_, result_type_) \
>   	XFULL(name_, query_type_, type_, result_type_, R600_QUERY_GROUP_##group_)
>   
>   static struct pipe_driver_query_info r600_driver_query_list[] = {
>   	X("num-compilations",		NUM_COMPILATIONS,	UINT64, CUMULATIVE),
>   	X("num-shaders-created",	NUM_SHADERS_CREATED,	UINT64, CUMULATIVE),
>   	X("num-shader-cache-hits",	NUM_SHADER_CACHE_HITS,	UINT64, CUMULATIVE),
>   	X("draw-calls",			DRAW_CALLS,		UINT64, AVERAGE),
> +	X("prim-restart-calls",		PRIM_RESTART_CALLS,	UINT64, AVERAGE),
>   	X("spill-draw-calls",		SPILL_DRAW_CALLS,	UINT64, AVERAGE),
>   	X("compute-calls",		COMPUTE_CALLS,		UINT64, AVERAGE),
>   	X("spill-compute-calls",	SPILL_COMPUTE_CALLS,	UINT64, AVERAGE),
>   	X("dma-calls",			DMA_CALLS,		UINT64, AVERAGE),
>   	X("cp-dma-calls",		CP_DMA_CALLS,		UINT64, AVERAGE),
>   	X("num-vs-flushes",		NUM_VS_FLUSHES,		UINT64, AVERAGE),
>   	X("num-ps-flushes",		NUM_PS_FLUSHES,		UINT64, AVERAGE),
>   	X("num-cs-flushes",		NUM_CS_FLUSHES,		UINT64, AVERAGE),
>   	X("num-fb-cache-flushes",	NUM_FB_CACHE_FLUSHES,	UINT64, AVERAGE),
>   	X("num-L2-invalidates",		NUM_L2_INVALIDATES,	UINT64, AVERAGE),
> diff --git a/src/gallium/drivers/radeon/r600_query.h b/src/gallium/drivers/radeon/r600_query.h
> index b9ab44c..05aceb7 100644
> --- a/src/gallium/drivers/radeon/r600_query.h
> +++ b/src/gallium/drivers/radeon/r600_query.h
> @@ -37,20 +37,21 @@ struct pipe_query;
>   struct pipe_resource;
>   
>   struct r600_common_context;
>   struct r600_common_screen;
>   struct r600_query;
>   struct r600_query_hw;
>   struct r600_resource;
>   
>   enum {
>   	R600_QUERY_DRAW_CALLS = PIPE_QUERY_DRIVER_SPECIFIC,
> +	R600_QUERY_PRIM_RESTART_CALLS,
>   	R600_QUERY_SPILL_DRAW_CALLS,
>   	R600_QUERY_COMPUTE_CALLS,
>   	R600_QUERY_SPILL_COMPUTE_CALLS,
>   	R600_QUERY_DMA_CALLS,
>   	R600_QUERY_CP_DMA_CALLS,
>   	R600_QUERY_NUM_VS_FLUSHES,
>   	R600_QUERY_NUM_PS_FLUSHES,
>   	R600_QUERY_NUM_CS_FLUSHES,
>   	R600_QUERY_NUM_FB_CACHE_FLUSHES,
>   	R600_QUERY_NUM_L2_INVALIDATES,
> diff --git a/src/gallium/drivers/radeonsi/si_state_draw.c b/src/gallium/drivers/radeonsi/si_state_draw.c
> index 2d5a08e..e6a9ee0 100644
> --- a/src/gallium/drivers/radeonsi/si_state_draw.c
> +++ b/src/gallium/drivers/radeonsi/si_state_draw.c
> @@ -1389,20 +1389,22 @@ void si_draw_vbo(struct pipe_context *ctx, const struct pipe_draw_info *info)
>   					rtex->dirty_level_mask |= 1 << surf->u.tex.level;
>   				if (rtex->dcc_gather_statistics)
>   					rtex->separate_dcc_dirty = true;
>   			} while (mask);
>   		}
>   		sctx->framebuffer.do_update_surf_dirtiness = false;
>   	}
>   
>   	pipe_resource_reference(&ib_tmp.buffer, NULL);
>   	sctx->b.num_draw_calls++;
> +	if (info->primitive_restart)
> +		sctx->b.num_prim_restart_calls++;
>   	if (G_0286E8_WAVESIZE(sctx->spi_tmpring_size))
>   		sctx->b.num_spill_draw_calls++;
>   }
>   
>   void si_trace_emit(struct si_context *sctx)
>   {
>   	struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
>   
>   	sctx->trace_id++;
>   	radeon_add_to_buffer_list(&sctx->b, &sctx->b.gfx, sctx->trace_buf,
> 


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