[Mesa-dev] [PATCH] i965: Set point rasterization rule to UPPER_RIGHT on Gen6-7.5.

[Kenneth Graunke]

Gen4-5 and Gen8+ already set this, but Gen6-7.5 did not.  We ought to
be consistent - the answer depends on the API, not the hardware generation.

The Sandybridge PRM says about RASTRULE_UPPER_RIGHT:

   "To match OpenGL point rasterization rules (round to +infinity, where
    this is the upper right direction wrt OpenGL screen origin of lower
    left).

So this is likely the one we should use.
---
 src/mesa/drivers/dri/i965/gen6_wm_state.c | 2 ++
 src/mesa/drivers/dri/i965/gen7_wm_state.c | 1 +
 2 files changed, 3 insertions(+)

diff --git a/src/mesa/drivers/dri/i965/gen6_wm_state.c b/src/mesa/drivers/dri/i965/gen6_wm_state.c
index aabae70d10b..2fb2a333853 100644
--- a/src/mesa/drivers/dri/i965/gen6_wm_state.c
+++ b/src/mesa/drivers/dri/i965/gen6_wm_state.c
@@ -199,6 +199,8 @@ gen6_upload_wm_state(struct brw_context *brw,
       dw6 |= GEN6_WM_MSDISPMODE_PERSAMPLE;
    }
 
+   dw6 |= GEN6_WM_POINT_RASTRULE_UPPER_RIGHT;
+
    /* From the SNB PRM, volume 2 part 1, page 281:
     * "If the PS kernel does not need the Position XY Offsets
     * to compute a Position XY value, then this field should be
diff --git a/src/mesa/drivers/dri/i965/gen7_wm_state.c b/src/mesa/drivers/dri/i965/gen7_wm_state.c
index 1c33db4d3b5..5efe55a0088 100644
--- a/src/mesa/drivers/dri/i965/gen7_wm_state.c
+++ b/src/mesa/drivers/dri/i965/gen7_wm_state.c
@@ -51,6 +51,7 @@ upload_wm_state(struct brw_context *brw)
    dw1 |= GEN7_WM_STATISTICS_ENABLE;
    dw1 |= GEN7_WM_LINE_AA_WIDTH_1_0;
    dw1 |= GEN7_WM_LINE_END_CAP_AA_WIDTH_0_5;
+   dw1 |= GEN7_WM_POINT_RASTRULE_UPPER_RIGHT;
 
    /* _NEW_LINE */
    if (ctx->Line.StippleFlag)
-- 
2.12.2