[Mesa-dev] [PATCH 53/61] radeonsi/gfx9: enable OpenGL 4.5

[Nicolai Hähnle]

I've sent comments on patches 43, 51, 52. Apart from those, patches 
37-53 are:

Reviewed-by: Nicolai Hähnle <nicolai.haehnle at amd.com>


On 24.04.2017 10:45, Marek Olšák wrote:
> From: Marek Olšák <marek.olsak at amd.com>
>
> Tentatively enable it, expecting the scratch buffer support to be done before
> the next Mesa release.
> ---
>  src/gallium/drivers/radeonsi/si_pipe.c | 5 -----
>  1 file changed, 5 deletions(-)
>
> diff --git a/src/gallium/drivers/radeonsi/si_pipe.c b/src/gallium/drivers/radeonsi/si_pipe.c
> index f0e24c2..1b013c4 100644
> --- a/src/gallium/drivers/radeonsi/si_pipe.c
> +++ b/src/gallium/drivers/radeonsi/si_pipe.c
> @@ -457,22 +457,20 @@ static int si_get_param(struct pipe_screen* pscreen, enum pipe_cap param)
>  	case PIPE_CAP_TEXTURE_BUFFER_OFFSET_ALIGNMENT:
>  	case PIPE_CAP_MAX_TEXTURE_GATHER_COMPONENTS:
>  	case PIPE_CAP_MAX_STREAM_OUTPUT_BUFFERS:
>  	case PIPE_CAP_MAX_VERTEX_STREAMS:
>  		return 4;
>
>  	case PIPE_CAP_SHADER_BUFFER_OFFSET_ALIGNMENT:
>  		return HAVE_LLVM >= 0x0309 ? 4 : 0;
>
>  	case PIPE_CAP_GLSL_FEATURE_LEVEL:
> -		if (sscreen->b.chip_class >= GFX9)
> -			return 140;
>  		if (si_have_tgsi_compute(sscreen))
>  			return 450;
>  		return HAVE_LLVM >= 0x0309 ? 420 : 410;
>
>  	case PIPE_CAP_MAX_TEXTURE_BUFFER_SIZE:
>  		return MIN2(sscreen->b.info.max_alloc_size, INT_MAX);
>
>  	case PIPE_CAP_VERTEX_BUFFER_OFFSET_4BYTE_ALIGNED_ONLY:
>  	case PIPE_CAP_VERTEX_BUFFER_STRIDE_4BYTE_ALIGNED_ONLY:
>  	case PIPE_CAP_VERTEX_ELEMENT_SRC_OFFSET_4BYTE_ALIGNED_ONLY:
> @@ -593,26 +591,23 @@ static int si_get_param(struct pipe_screen* pscreen, enum pipe_cap param)
>  static int si_get_shader_param(struct pipe_screen* pscreen,
>  			       enum pipe_shader_type shader,
>  			       enum pipe_shader_cap param)
>  {
>  	struct si_screen *sscreen = (struct si_screen *)pscreen;
>
>  	switch(shader)
>  	{
>  	case PIPE_SHADER_FRAGMENT:
>  	case PIPE_SHADER_VERTEX:
> -		break;
>  	case PIPE_SHADER_GEOMETRY:
>  	case PIPE_SHADER_TESS_CTRL:
>  	case PIPE_SHADER_TESS_EVAL:
> -		if (sscreen->b.chip_class >= GFX9)
> -			return 0;
>  		break;
>  	case PIPE_SHADER_COMPUTE:
>  		switch (param) {
>  		case PIPE_SHADER_CAP_PREFERRED_IR:
>  			return PIPE_SHADER_IR_NATIVE;
>
>  		case PIPE_SHADER_CAP_SUPPORTED_IRS: {
>  			int ir = 1 << PIPE_SHADER_IR_NATIVE;
>
>  			if (si_have_tgsi_compute(sscreen))
>


-- 
Lerne, wie die Welt wirklich ist,
Aber vergiss niemals, wie sie sein sollte.