[Mesa-dev] [PATCH 36/61] radeonsi/gfx9: set registers and shader key for merged ES-GS

[Marek Olšák]

On Fri, Apr 28, 2017 at 9:31 PM, Nicolai Hähnle <nhaehnle at gmail.com> wrote:
> Fair enough on those magic numbers. It would be nice to understand them
> better though.
>
>
> On 28.04.2017 17:56, Marek Olšák wrote:
> [snip]
>>>>
>>>> @@ -1721,20 +1893,26 @@ static void *si_create_shader_selector(struct
>>>> pipe_context *ctx,
>>>>                                 break;
>>>>                         case TGSI_SEMANTIC_CLIPVERTEX: /* ignore these
>>>> */
>>>>                         case TGSI_SEMANTIC_EDGEFLAG:
>>>>                                 break;
>>>>                         default:
>>>>                                 sel->outputs_written2 |=
>>>>                                         1u <<
>>>> si_shader_io_get_unique_index2(name, index);
>>>>                         }
>>>>                 }
>>>>                 sel->esgs_itemsize =
>>>> util_last_bit64(sel->outputs_written)
>>>> * 16;
>>>> +
>>>> +               /* For the ESGS ring in LDS, add 1 dword to reduce LDS
>>>> bank
>>>> +                * conflicts, i.e. each vertex will start at a different
>>>> bank.
>>>> +                */
>>>> +               if (sctx->b.chip_class >= GFX9)
>>>> +                       sel->esgs_itemsize += 4;
>>>
>>>
>>>
>>> Could this not be achieved by some form of rounding instead?
>>
>>
>> What do you mean?
>
>
> Actually, I think I was mistaken. There are 4 banks, and they're
> interleaved, right? So the idea is to have esgs_itemsize not be a multiple
> of 16 bytes, but a multiple of 16 bytes + 4 bytes. It makes sense to me now.

As far as I know, LDS has 32 banks, but some small chips (Kabini,
Stoney) have only 16 banks. I don't know how they are interleaved.
This tweak was suggested by a hw doc.

Marek