[Mesa-dev] [PATCH] nv50/ir: we can't replace 0x0 with zero reg for SHLADD

[Karol Herbst]

2017-04-29 17:18 GMT+02:00 Ilia Mirkin <imirkin at alum.mit.edu>:
> On Sat, Apr 29, 2017 at 10:41 AM, Karol Herbst <karolherbst at gmail.com> wrote:
>> fixes a crash in Alien Isolation
>
> What crash?

assertion, because shladd requires an immediate, there can't be a reg at src1

"shladd u32 $r0 $r0 $r63 $r36" is invalid for the emiter so we have to
use 0x0 here

> How did the zero get there?

by replaceZero

> Does this only happen if you do your optimization loop thing?

no, it happens on master and the stable branches without any modifications

>
> In either case, we still want the replaceZero() logic. However that
> logic should be aware that the middle argument of a SHLADD is not to
> be touched. Otherwise we could end up with an un-emittable
> instruction.

ohh right, you mean for the other args... true.

>
>>
>> Signed-off-by: Karol Herbst <karolherbst at gmail.com>
>> ---
>>  src/gallium/drivers/nouveau/codegen/nv50_ir_lowering_nvc0.cpp | 2 +-
>>  1 file changed, 1 insertion(+), 1 deletion(-)
>>
>> diff --git a/src/gallium/drivers/nouveau/codegen/nv50_ir_lowering_nvc0.cpp b/src/gallium/drivers/nouveau/codegen/nv50_ir_lowering_nvc0.cpp
>> index 732e1a93b4..4815d6df07 100644
>> --- a/src/gallium/drivers/nouveau/codegen/nv50_ir_lowering_nvc0.cpp
>> +++ b/src/gallium/drivers/nouveau/codegen/nv50_ir_lowering_nvc0.cpp
>> @@ -740,7 +740,7 @@ NVC0LegalizePostRA::visit(BasicBlock *bb)
>>                 next = hi;
>>           }
>>
>> -         if (i->op != OP_MOV && i->op != OP_PFETCH)
>> +         if (i->op != OP_MOV && i->op != OP_PFETCH && i->op != OP_SHLADD)
>>              replaceZero(i);
>>        }
>>     }
>> --
>> 2.12.2
>>