[Mesa-dev] [PATCH 1/6] radeonsi: fix various CLEAR_STATE issues

[Marek Olšák]

On Tue, Aug 1, 2017 at 2:40 PM, Nicolai Hähnle <nhaehnle at gmail.com> wrote:
> On 01.08.2017 00:43, Marek Olšák wrote:
>>
>> From: Marek Olšák <marek.olsak at amd.com>
>>
>> ---
>>   src/gallium/drivers/radeonsi/si_state.c | 22 ++++++++++++++++++++++
>>   1 file changed, 22 insertions(+)
>>
>> diff --git a/src/gallium/drivers/radeonsi/si_state.c
>> b/src/gallium/drivers/radeonsi/si_state.c
>> index 7dadc4a..c151a98 100644
>> --- a/src/gallium/drivers/radeonsi/si_state.c
>> +++ b/src/gallium/drivers/radeonsi/si_state.c
>> @@ -4542,24 +4542,46 @@ static void si_init_config(struct si_context
>> *sctx)
>>                         si_pm4_set_reg(pm4, R_028350_PA_SC_RASTER_CONFIG,
>>                                        raster_config);
>>                         if (sctx->b.chip_class >= CIK)
>>                                 si_pm4_set_reg(pm4,
>> R_028354_PA_SC_RASTER_CONFIG_1,
>>                                                raster_config_1);
>>                 } else {
>>                         si_write_harvested_raster_configs(sctx, pm4,
>> raster_config, raster_config_1);
>>                 }
>>         }
>>   +     /* CLEAR_STATE doesn't clear these correctly on certain
>> generations.
>> +        * I don't know why. Deduced by trial and error.
>> +        */
>> +       if (sctx->b.chip_class <= CIK) {
>> +               si_pm4_set_reg(pm4,
>> R_028B28_VGT_STRMOUT_DRAW_OPAQUE_OFFSET, 0);
>
>
> This one moved from IA to WD in CI for 4SE configurations. Maybe it's
> related to that? Unless you specifically verified that this one causes fail

I tested this on Hawaii and then just verified than Cape Verde works too.

Marek