[Mesa-dev] [PATCH v2 4/6] radeonsi: add si_emit_graphics_shader_pointers() helper

[Marek Olšák]

On Wed, Jul 26, 2017 at 4:21 PM, Samuel Pitoiset
<samuel.pitoiset at gmail.com> wrote:
> To share common code between rw buffers and bindless descriptors.
>
> Signed-off-by: Samuel Pitoiset <samuel.pitoiset at gmail.com>
> ---
>  src/gallium/drivers/radeonsi/si_descriptors.c | 57 +++++++++++++++------------
>  1 file changed, 31 insertions(+), 26 deletions(-)
>
> diff --git a/src/gallium/drivers/radeonsi/si_descriptors.c b/src/gallium/drivers/radeonsi/si_descriptors.c
> index 91204f0102..06a171ff9e 100644
> --- a/src/gallium/drivers/radeonsi/si_descriptors.c
> +++ b/src/gallium/drivers/radeonsi/si_descriptors.c
> @@ -2162,6 +2162,35 @@ static void si_emit_shader_pointer(struct si_context *sctx,
>         radeon_emit(cs, va >> 32);
>  }
>
> +static void si_emit_graphics_shader_pointers(struct si_context *sctx,
> +                                            struct si_descriptors *descs)
> +{
> +       si_emit_shader_pointer(sctx, descs,
> +                              R_00B030_SPI_SHADER_USER_DATA_PS_0);
> +       si_emit_shader_pointer(sctx, descs,
> +                              R_00B130_SPI_SHADER_USER_DATA_VS_0);
> +
> +       if (sctx->b.chip_class >= GFX9) {
> +               /* GFX9 merged LS-HS and ES-GS.
> +                * Set RW_BUFFERS in the special registers, so that
> +                * it's preloaded into s[0:1] instead of s[8:9].
> +                */
> +               si_emit_shader_pointer(sctx, descs,
> +                                      R_00B208_SPI_SHADER_USER_DATA_ADDR_LO_GS);
> +               si_emit_shader_pointer(sctx, descs,
> +                                      R_00B408_SPI_SHADER_USER_DATA_ADDR_LO_HS);

This GFX9 code is not reusable. SPI_SHADER_USER_DATA_ADDR_LO & HI
refer to exactly 2 SGPRs and there are no other user SGPRs around
that. This is how SGPRs are loaded for GFX9 HS and GS stages:

s0 = SPI_SHADER_USER_DATA_ADDR_LO_GS/HS
s1 = SPI_SHADER_USER_DATA_ADDR_HI_GS/HS
s2 = hw-specific system values
s3 = hw-specific system values
s4 = hw-specific system values
s5 = hw-specific system values
s6 = (SPI_SHADER_PGM_LO+HI_GS/HS << 8)
s7 = (SPI_SHADER_PGM_LO+HI_GS/HS << 8) >> 32
s8 = SPI_SHADER_USER_DATA_ES/LS_0
...
s39 = SPI_SHADER_USER_DATA_ES/LS_31

That should explain the layout for SI_SHADER_MERGED_VERTEX_*. I admit
it wasn't properly documented.

Marek