[Mesa-dev] [PATCH] i965: Allow manual detiled uploads on !llc

[Chris Wilson]

With WC support, we can also use our manual detiling paths for !llc
architectures as well. This is even more important for those as the
indirection of the GTT is even more significant.

Currently, we can only effectively support WC uploads into X-tiling, as
we have to uploading into Y is slower than using the GTT (as each
sequential write misses the WCB, completely nerfing its performance.)
However, supporting X tiling is useful for scanouts (glamor, ahem).

Cc: Kenneth Graunke <kenneth at whitecape.org>
Cc: Matt Turner <mattst88 at gmail.com>
---
 src/mesa/drivers/dri/i965/intel_tex_subimage.c | 13 +++++++++----
 1 file changed, 9 insertions(+), 4 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/intel_tex_subimage.c b/src/mesa/drivers/dri/i965/intel_tex_subimage.c
index 5953e61ec2..a34203087f 100644
--- a/src/mesa/drivers/dri/i965/intel_tex_subimage.c
+++ b/src/mesa/drivers/dri/i965/intel_tex_subimage.c
@@ -98,8 +98,7 @@ intel_texsubimage_tiled_memcpy(struct gl_context * ctx,
     * with _mesa_image_row_stride. However, before removing the restrictions
     * we need tests.
     */
-   if (!brw->has_llc ||
-       !(type == GL_UNSIGNED_BYTE || type == GL_UNSIGNED_INT_8_8_8_8_REV) ||
+   if (!(type == GL_UNSIGNED_BYTE || type == GL_UNSIGNED_INT_8_8_8_8_REV) ||
        !(texImage->TexObject->Target == GL_TEXTURE_2D ||
          texImage->TexObject->Target == GL_TEXTURE_RECTANGLE) ||
        pixels == NULL ||
@@ -145,6 +144,14 @@ intel_texsubimage_tiled_memcpy(struct gl_context * ctx,
    if (brw->gen < 5 && brw->has_swizzling)
       return false;
 
+   bo = image->mt->bo;
+
+   /* Uploading into Y-tiling surfaces using WC is slow as each sequential
+    * write falls outside of the WCB, completely nerfing the WC performance.
+    */
+   if (!bo->cache_coherent && image->mt->surf.tiling == ISL_TILING_Y0)
+      return false;
+
    int level = texImage->Level + texImage->TexObject->MinLevel;
 
    /* Since we are going to write raw data to the miptree, we need to resolve
@@ -155,8 +162,6 @@ intel_texsubimage_tiled_memcpy(struct gl_context * ctx,
 
    intel_miptree_access_raw(brw, image->mt, level, 0, true);
 
-   bo = image->mt->bo;
-
    if (brw_batch_references(&brw->batch, bo)) {
       perf_debug("Flushing before mapping a referenced bo.\n");
       intel_batchbuffer_flush(brw);
-- 
2.13.3