[Mesa-dev] [PATCH 03/11] i965/blit: Stop asserting linear row_pitches are 64B-aligned

[Jason Ekstrand]

The 64B alignment restriction is on the base address and not the row
pitch.  This code already ensures that the base address is aligned by
adding a small X offset if needed.  The assertion serves no purpose and
is actually causing people problems.

Cc: "17.2" <mesa-stable at lists.freedesktop.org>
Cc: Kenneth Graunke <kenneth at whitecape.org>
---
 src/mesa/drivers/dri/i965/intel_blit.c | 1 -
 1 file changed, 1 deletion(-)

diff --git a/src/mesa/drivers/dri/i965/intel_blit.c b/src/mesa/drivers/dri/i965/intel_blit.c
index eca8736..b1db7aa 100644
--- a/src/mesa/drivers/dri/i965/intel_blit.c
+++ b/src/mesa/drivers/dri/i965/intel_blit.c
@@ -187,7 +187,6 @@ get_blit_intratile_offset_el(const struct brw_context *brw,
        * The offsets we get from ISL in the tiled case are already aligned.
        * In the linear case, we need to do some of our own aligning.
        */
-      assert(mt->surf.row_pitch % 64 == 0);
       uint32_t delta = *base_address_offset & 63;
       assert(delta % mt->cpp == 0);
       *base_address_offset -= delta;
-- 
2.5.0.400.gff86faf