[Mesa-dev] [PATCH 11/11] i965/miptree: Rework create flags
Jason Ekstrand
jason at jlekstrand.net
Wed Aug 2 20:35:36 UTC 2017
The only one of the three remaining flags that has anything whatsoever
to do with layout is TILING_NONE. This commit renames them to
MIPTREE_CREATE_*, documents the meaning of each flag, and makes the
create functions take an actual enum type so GDB will print them nicely.
---
src/mesa/drivers/dri/i965/brw_context.c | 2 +-
src/mesa/drivers/dri/i965/intel_fbo.c | 4 +--
src/mesa/drivers/dri/i965/intel_mipmap_tree.c | 38 ++++++++++++--------------
src/mesa/drivers/dri/i965/intel_mipmap_tree.h | 30 ++++++++++++++++----
src/mesa/drivers/dri/i965/intel_pixel_draw.c | 2 +-
src/mesa/drivers/dri/i965/intel_tex.c | 4 +--
src/mesa/drivers/dri/i965/intel_tex_image.c | 7 +++--
src/mesa/drivers/dri/i965/intel_tex_validate.c | 3 +-
8 files changed, 52 insertions(+), 38 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_context.c b/src/mesa/drivers/dri/i965/brw_context.c
index c3c4d80..60b1457 100644
--- a/src/mesa/drivers/dri/i965/brw_context.c
+++ b/src/mesa/drivers/dri/i965/brw_context.c
@@ -1518,7 +1518,7 @@ intel_process_dri2_buffer(struct brw_context *brw,
drawable->h,
1,
buffer->pitch,
- 0);
+ MIPTREE_CREATE_DEFAULT);
if (!mt) {
brw_bo_unreference(bo);
return;
diff --git a/src/mesa/drivers/dri/i965/intel_fbo.c b/src/mesa/drivers/dri/i965/intel_fbo.c
index 71bc90d..ca80b96 100644
--- a/src/mesa/drivers/dri/i965/intel_fbo.c
+++ b/src/mesa/drivers/dri/i965/intel_fbo.c
@@ -944,8 +944,6 @@ intel_renderbuffer_move_to_temp(struct brw_context *brw,
struct intel_mipmap_tree *new_mt;
int width, height, depth;
- uint32_t layout_flags = MIPTREE_LAYOUT_ACCELERATED_UPLOAD;
-
intel_get_image_dims(rb->TexImage, &width, &height, &depth);
assert(irb->align_wa_mt == NULL);
@@ -954,7 +952,7 @@ intel_renderbuffer_move_to_temp(struct brw_context *brw,
0, 0,
width, height, 1,
irb->mt->surf.samples,
- layout_flags);
+ MIPTREE_CREATE_BUSY);
if (!invalidate)
intel_miptree_copy_slice(brw, intel_image->mt,
diff --git a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
index 7e87099..17ac563 100644
--- a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
+++ b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
@@ -638,7 +638,7 @@ miptree_create(struct brw_context *brw,
GLuint height0,
GLuint depth0,
GLuint num_samples,
- uint32_t layout_flags)
+ enum intel_miptree_create_flags flags)
{
if (format == MESA_FORMAT_S_UINT8)
return make_surface(brw, target, format, first_level, last_level,
@@ -653,7 +653,7 @@ miptree_create(struct brw_context *brw,
const GLenum base_format = _mesa_get_format_base_format(format);
if ((base_format == GL_DEPTH_COMPONENT ||
base_format == GL_DEPTH_STENCIL) &&
- !(layout_flags & MIPTREE_LAYOUT_TILING_NONE)) {
+ !(flags & MIPTREE_CREATE_LINEAR)) {
/* Fix up the Z miptree format for how we're splitting out separate
* stencil. Gen7 expects there to be no stencil bits in its depth buffer.
*/
@@ -672,7 +672,7 @@ miptree_create(struct brw_context *brw,
return NULL;
}
- if (!(layout_flags & MIPTREE_LAYOUT_DISABLE_AUX))
+ if (!(flags & MIPTREE_CREATE_NO_AUX))
intel_miptree_choose_aux_usage(brw, mt);
return mt;
@@ -686,11 +686,10 @@ miptree_create(struct brw_context *brw,
etc_format = (format != tex_format) ? tex_format : MESA_FORMAT_NONE;
- if (layout_flags & MIPTREE_LAYOUT_ACCELERATED_UPLOAD)
+ if (flags & MIPTREE_CREATE_BUSY)
alloc_flags |= BO_ALLOC_FOR_RENDER;
- isl_tiling_flags_t tiling_flags =
- (layout_flags & MIPTREE_LAYOUT_TILING_NONE) ?
+ isl_tiling_flags_t tiling_flags = (flags & MIPTREE_CREATE_LINEAR) ?
ISL_TILING_LINEAR_BIT : ISL_TILING_ANY_MASK;
/* TODO: This used to be because there wasn't BLORP to handle Y-tiling. */
@@ -710,7 +709,7 @@ miptree_create(struct brw_context *brw,
mt->etc_format = etc_format;
- if (!(layout_flags & MIPTREE_LAYOUT_DISABLE_AUX))
+ if (!(flags & MIPTREE_CREATE_NO_AUX))
intel_miptree_choose_aux_usage(brw, mt);
return mt;
@@ -726,7 +725,7 @@ intel_miptree_create(struct brw_context *brw,
GLuint height0,
GLuint depth0,
GLuint num_samples,
- uint32_t layout_flags)
+ enum intel_miptree_create_flags flags)
{
assert(num_samples > 0);
@@ -734,7 +733,7 @@ intel_miptree_create(struct brw_context *brw,
brw, target, format,
first_level, last_level,
width0, height0, depth0, num_samples,
- layout_flags);
+ flags);
if (!mt)
return NULL;
@@ -757,7 +756,7 @@ intel_miptree_create_for_bo(struct brw_context *brw,
uint32_t height,
uint32_t depth,
int pitch,
- uint32_t layout_flags)
+ enum intel_miptree_create_flags flags)
{
struct intel_mipmap_tree *mt;
uint32_t tiling, swizzle;
@@ -778,7 +777,7 @@ intel_miptree_create_for_bo(struct brw_context *brw,
brw_bo_reference(bo);
- if (!(layout_flags & MIPTREE_LAYOUT_DISABLE_AUX))
+ if (!(flags & MIPTREE_CREATE_NO_AUX))
intel_miptree_choose_aux_usage(brw, mt);
return mt;
@@ -814,7 +813,7 @@ intel_miptree_create_for_bo(struct brw_context *brw,
/* The BO already has a tiling format and we shouldn't confuse the lower
* layers by making it try to find a tiling format again.
*/
- assert((layout_flags & MIPTREE_LAYOUT_TILING_NONE) == 0);
+ assert((flags & MIPTREE_CREATE_LINEAR) == 0);
mt = make_surface(brw, target, format,
0, 0, width, height, depth, 1,
@@ -829,7 +828,7 @@ intel_miptree_create_for_bo(struct brw_context *brw,
mt->bo = bo;
mt->offset = offset;
- if (!(layout_flags & MIPTREE_LAYOUT_DISABLE_AUX)) {
+ if (!(flags & MIPTREE_CREATE_NO_AUX)) {
intel_miptree_choose_aux_usage(brw, mt);
if (!intel_miptree_alloc_aux(brw, mt)) {
@@ -865,7 +864,7 @@ miptree_create_for_planar_image(struct brw_context *brw,
image->offsets[index],
width, height, 1,
image->strides[index],
- MIPTREE_LAYOUT_DISABLE_AUX);
+ MIPTREE_CREATE_NO_AUX);
if (mt == NULL)
return NULL;
@@ -933,8 +932,8 @@ intel_miptree_create_for_dri_image(struct brw_context *brw,
* have the opportunity to do resolves. Window system buffers also may be
* used for scanout so we need to flag that appropriately.
*/
- const uint32_t mt_layout_flags =
- is_winsys_image ? 0 : MIPTREE_LAYOUT_DISABLE_AUX;
+ const enum intel_miptree_create_flags mt_create_flags =
+ is_winsys_image ? 0 : MIPTREE_CREATE_NO_AUX;
/* Disable creation of the texture's aux buffers because the driver exposes
* no EGL API to manage them. That is, there is no API for resolving the aux
@@ -944,7 +943,7 @@ intel_miptree_create_for_dri_image(struct brw_context *brw,
struct intel_mipmap_tree *mt =
intel_miptree_create_for_bo(brw, image->bo, format,
image->offset, image->width, image->height, 1,
- image->pitch, mt_layout_flags);
+ image->pitch, mt_create_flags);
if (mt == NULL)
return NULL;
@@ -1049,11 +1048,10 @@ intel_miptree_create_for_renderbuffer(struct brw_context *brw,
struct intel_mipmap_tree *mt;
uint32_t depth = 1;
GLenum target = num_samples > 1 ? GL_TEXTURE_2D_MULTISAMPLE : GL_TEXTURE_2D;
- const uint32_t layout_flags = MIPTREE_LAYOUT_ACCELERATED_UPLOAD;
mt = intel_miptree_create(brw, target, format, 0, 0,
width, height, depth, num_samples,
- layout_flags);
+ MIPTREE_CREATE_BUSY);
if (!mt)
goto fail;
@@ -2941,7 +2939,7 @@ intel_miptree_map_blit(struct brw_context *brw,
/* last_level */ 0,
map->w, map->h, 1,
/* samples */ 1,
- MIPTREE_LAYOUT_TILING_NONE);
+ MIPTREE_CREATE_LINEAR);
if (!map->linear_mt) {
fprintf(stderr, "Failed to allocate blit temporary\n");
diff --git a/src/mesa/drivers/dri/i965/intel_mipmap_tree.h b/src/mesa/drivers/dri/i965/intel_mipmap_tree.h
index 28e8e01..d9d693d 100644
--- a/src/mesa/drivers/dri/i965/intel_mipmap_tree.h
+++ b/src/mesa/drivers/dri/i965/intel_mipmap_tree.h
@@ -348,11 +348,29 @@ bool
intel_miptree_alloc_ccs(struct brw_context *brw,
struct intel_mipmap_tree *mt);
-enum {
- MIPTREE_LAYOUT_ACCELERATED_UPLOAD = 1 << 0,
- MIPTREE_LAYOUT_DISABLE_AUX = 1 << 3,
+enum intel_miptree_create_flags {
+ /** No miptree create flags */
+ MIPTREE_CREATE_DEFAULT = 0,
- MIPTREE_LAYOUT_TILING_NONE = 1 << 6,
+ /** Miptree creation should try to allocate a currently busy BO
+ *
+ * This may be advantageous if we know the next thing to touch the BO will
+ * be the GPU because the BO will likely already be in the GTT and maybe
+ * even in some caches. If there is a chance that the next thing to touch
+ * the miptree BO will be the CPU, this flag should not be set.
+ */
+ MIPTREE_CREATE_BUSY = 1 << 0,
+
+ /** Create a linear (not tiled) miptree */
+ MIPTREE_CREATE_LINEAR = 1 << 1,
+
+ /** Create the miptree with auxiliary compression disabled
+ *
+ * This does not prevent the caller of intel_miptree_create from coming
+ * along later and turning auxiliary compression back on but it does mean
+ * that the miptree will be created with mt->aux_usage == NONE.
+ */
+ MIPTREE_CREATE_NO_AUX = 1 << 2,
};
struct intel_mipmap_tree *intel_miptree_create(struct brw_context *brw,
@@ -364,7 +382,7 @@ struct intel_mipmap_tree *intel_miptree_create(struct brw_context *brw,
GLuint height0,
GLuint depth0,
GLuint num_samples,
- uint32_t flags);
+ enum intel_miptree_create_flags flags);
struct intel_mipmap_tree *
intel_miptree_create_for_bo(struct brw_context *brw,
@@ -375,7 +393,7 @@ intel_miptree_create_for_bo(struct brw_context *brw,
uint32_t height,
uint32_t depth,
int pitch,
- uint32_t layout_flags);
+ enum intel_miptree_create_flags flags);
struct intel_mipmap_tree *
intel_miptree_create_for_dri_image(struct brw_context *brw,
diff --git a/src/mesa/drivers/dri/i965/intel_pixel_draw.c b/src/mesa/drivers/dri/i965/intel_pixel_draw.c
index 519e059..81299da 100644
--- a/src/mesa/drivers/dri/i965/intel_pixel_draw.c
+++ b/src/mesa/drivers/dri/i965/intel_pixel_draw.c
@@ -118,7 +118,7 @@ do_blit_drawpixels(struct gl_context * ctx,
src_offset,
width, height, 1,
src_stride,
- 0);
+ MIPTREE_CREATE_DEFAULT);
if (!pbo_mt)
return false;
diff --git a/src/mesa/drivers/dri/i965/intel_tex.c b/src/mesa/drivers/dri/i965/intel_tex.c
index 686b31c..890c82d 100644
--- a/src/mesa/drivers/dri/i965/intel_tex.c
+++ b/src/mesa/drivers/dri/i965/intel_tex.c
@@ -150,7 +150,7 @@ intel_alloc_texture_storage(struct gl_context *ctx,
0, levels - 1,
width, height, depth,
MAX2(num_samples, 1),
- 0);
+ MIPTREE_CREATE_DEFAULT);
if (intel_texobj->mt == NULL) {
return false;
@@ -345,7 +345,7 @@ intel_set_texture_storage_for_buffer_object(struct gl_context *ctx,
buffer_offset,
image->Width, image->Height, image->Depth,
row_stride,
- 0);
+ MIPTREE_CREATE_DEFAULT);
if (!intel_texobj->mt)
return false;
diff --git a/src/mesa/drivers/dri/i965/intel_tex_image.c b/src/mesa/drivers/dri/i965/intel_tex_image.c
index 598d39c..298a256 100644
--- a/src/mesa/drivers/dri/i965/intel_tex_image.c
+++ b/src/mesa/drivers/dri/i965/intel_tex_image.c
@@ -52,7 +52,7 @@ struct intel_mipmap_tree *
intel_miptree_create_for_teximage(struct brw_context *brw,
struct intel_texture_object *intelObj,
struct intel_texture_image *intelImage,
- uint32_t layout_flags)
+ enum intel_miptree_create_flags flags)
{
GLuint lastLevel;
int width, height, depth;
@@ -124,7 +124,7 @@ intel_miptree_create_for_teximage(struct brw_context *brw,
height,
depth,
MAX2(intelImage->base.Base.NumSamples, 1),
- layout_flags);
+ flags);
}
static void
@@ -261,7 +261,8 @@ intelSetTexBuffer2(__DRIcontext *pDRICtx, GLint target,
mt = intel_miptree_create_for_bo(brw, rb->mt->bo, texFormat, 0,
rb->Base.Base.Width,
rb->Base.Base.Height,
- 1, rb->mt->surf.row_pitch, 0);
+ 1, rb->mt->surf.row_pitch,
+ MIPTREE_CREATE_DEFAULT);
if (mt == NULL)
return;
mt->target = target;
diff --git a/src/mesa/drivers/dri/i965/intel_tex_validate.c b/src/mesa/drivers/dri/i965/intel_tex_validate.c
index 1e735c9..16354d2 100644
--- a/src/mesa/drivers/dri/i965/intel_tex_validate.c
+++ b/src/mesa/drivers/dri/i965/intel_tex_validate.c
@@ -136,7 +136,6 @@ intel_finalize_mipmap_tree(struct brw_context *brw, GLuint unit)
_mesa_get_format_name(firstImage->base.Base.TexFormat),
width, height, depth, validate_last_level + 1);
- const uint32_t layout_flags = MIPTREE_LAYOUT_ACCELERATED_UPLOAD;
intelObj->mt = intel_miptree_create(brw,
intelObj->base.Target,
firstImage->base.Base.TexFormat,
@@ -146,7 +145,7 @@ intel_finalize_mipmap_tree(struct brw_context *brw, GLuint unit)
height,
depth,
1 /* num_samples */,
- layout_flags);
+ MIPTREE_CREATE_BUSY);
if (!intelObj->mt)
return;
}
--
2.5.0.400.gff86faf
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