[Mesa-dev] [PATCH 13/25] i965: Extract functions dealing with register types to separate file

Matt Turner mattst88 at gmail.com
Fri Aug 4 17:31:45 UTC 2017


I'm going to encapsulate all of the logic dealing with register types in
this file.

Rename the parameters for the hardware encodings from type -> hw_type at
the same time.
---
 src/intel/Makefile.sources        |   2 +
 src/intel/compiler/brw_eu_emit.c  | 102 ------------------------------
 src/intel/compiler/brw_reg.h      |  35 +----------
 src/intel/compiler/brw_reg_type.c | 128 ++++++++++++++++++++++++++++++++++++++
 src/intel/compiler/brw_reg_type.h |  74 ++++++++++++++++++++++
 5 files changed, 205 insertions(+), 136 deletions(-)
 create mode 100644 src/intel/compiler/brw_reg_type.c
 create mode 100644 src/intel/compiler/brw_reg_type.h

diff --git a/src/intel/Makefile.sources b/src/intel/Makefile.sources
index 5d8785832f..4074ba9ee5 100644
--- a/src/intel/Makefile.sources
+++ b/src/intel/Makefile.sources
@@ -81,6 +81,8 @@ COMPILER_FILES = \
 	compiler/brw_packed_float.c \
 	compiler/brw_predicated_break.cpp \
 	compiler/brw_reg.h \
+	compiler/brw_reg_type.c \
+	compiler/brw_reg_type.h \
 	compiler/brw_schedule_instructions.cpp \
 	compiler/brw_shader.cpp \
 	compiler/brw_shader.h \
diff --git a/src/intel/compiler/brw_eu_emit.c b/src/intel/compiler/brw_eu_emit.c
index 12e9d332a1..133a28e1bf 100644
--- a/src/intel/compiler/brw_eu_emit.c
+++ b/src/intel/compiler/brw_eu_emit.c
@@ -84,108 +84,6 @@ gen7_convert_mrf_to_grf(struct brw_codegen *p, struct brw_reg *reg)
    }
 }
 
-/**
- * Convert a brw_reg_type enumeration value into the hardware representation.
- *
- * The hardware encoding may depend on whether the value is an immediate.
- */
-unsigned
-brw_reg_type_to_hw_type(const struct gen_device_info *devinfo,
-                        enum brw_reg_file file,
-                        enum brw_reg_type type)
-{
-   if (file == BRW_IMMEDIATE_VALUE) {
-      static const enum hw_imm_type hw_types[] = {
-         [0 ... BRW_REGISTER_TYPE_LAST] = -1,
-         [BRW_REGISTER_TYPE_UD] = BRW_HW_IMM_TYPE_UD,
-         [BRW_REGISTER_TYPE_D]  = BRW_HW_IMM_TYPE_D,
-         [BRW_REGISTER_TYPE_UW] = BRW_HW_IMM_TYPE_UW,
-         [BRW_REGISTER_TYPE_W]  = BRW_HW_IMM_TYPE_W,
-         [BRW_REGISTER_TYPE_F]  = BRW_HW_IMM_TYPE_F,
-         [BRW_REGISTER_TYPE_UV] = BRW_HW_IMM_TYPE_UV,
-         [BRW_REGISTER_TYPE_VF] = BRW_HW_IMM_TYPE_VF,
-         [BRW_REGISTER_TYPE_V]  = BRW_HW_IMM_TYPE_V,
-         [BRW_REGISTER_TYPE_DF] = GEN8_HW_IMM_TYPE_DF,
-         [BRW_REGISTER_TYPE_HF] = GEN8_HW_IMM_TYPE_HF,
-         [BRW_REGISTER_TYPE_UQ] = GEN8_HW_IMM_TYPE_UQ,
-         [BRW_REGISTER_TYPE_Q]  = GEN8_HW_IMM_TYPE_Q,
-      };
-      assert(type < ARRAY_SIZE(hw_types));
-      assert(hw_types[type] != -1);
-      return hw_types[type];
-   } else {
-      /* Non-immediate registers */
-      static const enum hw_reg_type hw_types[] = {
-         [0 ... BRW_REGISTER_TYPE_LAST] = -1,
-         [BRW_REGISTER_TYPE_UD] = BRW_HW_REG_TYPE_UD,
-         [BRW_REGISTER_TYPE_D]  = BRW_HW_REG_TYPE_D,
-         [BRW_REGISTER_TYPE_UW] = BRW_HW_REG_TYPE_UW,
-         [BRW_REGISTER_TYPE_W]  = BRW_HW_REG_TYPE_W,
-         [BRW_REGISTER_TYPE_UB] = BRW_HW_REG_TYPE_UB,
-         [BRW_REGISTER_TYPE_B]  = BRW_HW_REG_TYPE_B,
-         [BRW_REGISTER_TYPE_F]  = BRW_HW_REG_TYPE_F,
-         [BRW_REGISTER_TYPE_DF] = GEN7_HW_REG_TYPE_DF,
-         [BRW_REGISTER_TYPE_HF] = GEN8_HW_REG_TYPE_HF,
-         [BRW_REGISTER_TYPE_UQ] = GEN8_HW_REG_TYPE_UQ,
-         [BRW_REGISTER_TYPE_Q]  = GEN8_HW_REG_TYPE_Q,
-      };
-      assert(type < ARRAY_SIZE(hw_types));
-      assert(hw_types[type] != -1);
-      return hw_types[type];
-   }
-}
-
-/**
- * Return the element size given a hardware register type and file.
- *
- * The hardware encoding may depend on whether the value is an immediate.
- */
-unsigned
-brw_hw_reg_type_to_size(const struct gen_device_info *devinfo,
-                        enum brw_reg_file file,
-                        unsigned type)
-{
-   if (file == BRW_IMMEDIATE_VALUE) {
-      static const int hw_sizes[] = {
-         [0 ... 15]            = -1,
-         [BRW_HW_IMM_TYPE_UD]  = 4,
-         [BRW_HW_IMM_TYPE_D]   = 4,
-         [BRW_HW_IMM_TYPE_UW]  = 2,
-         [BRW_HW_IMM_TYPE_W]   = 2,
-         [BRW_HW_IMM_TYPE_UV]  = 2,
-         [BRW_HW_IMM_TYPE_VF]  = 4,
-         [BRW_HW_IMM_TYPE_V]   = 2,
-         [BRW_HW_IMM_TYPE_F]   = 4,
-         [GEN8_HW_IMM_TYPE_UQ] = 8,
-         [GEN8_HW_IMM_TYPE_Q]  = 8,
-         [GEN8_HW_IMM_TYPE_DF] = 8,
-         [GEN8_HW_IMM_TYPE_HF] = 2,
-      };
-      assert(type < ARRAY_SIZE(hw_sizes));
-      assert(hw_sizes[type] != -1);
-      return hw_sizes[type];
-   } else {
-      /* Non-immediate registers */
-      static const int hw_sizes[] = {
-         [0 ... 15]            = -1,
-         [BRW_HW_REG_TYPE_UD]  = 4,
-         [BRW_HW_REG_TYPE_D]   = 4,
-         [BRW_HW_REG_TYPE_UW]  = 2,
-         [BRW_HW_REG_TYPE_W]   = 2,
-         [BRW_HW_REG_TYPE_UB]  = 1,
-         [BRW_HW_REG_TYPE_B]   = 1,
-         [GEN7_HW_REG_TYPE_DF] = 8,
-         [BRW_HW_REG_TYPE_F]   = 4,
-         [GEN8_HW_REG_TYPE_UQ] = 8,
-         [GEN8_HW_REG_TYPE_Q]  = 8,
-         [GEN8_HW_REG_TYPE_HF] = 2,
-      };
-      assert(type < ARRAY_SIZE(hw_sizes));
-      assert(hw_sizes[type] != -1);
-      return hw_sizes[type];
-   }
-}
-
 void
 brw_set_dest(struct brw_codegen *p, brw_inst *inst, struct brw_reg dest)
 {
diff --git a/src/intel/compiler/brw_reg.h b/src/intel/compiler/brw_reg.h
index db932cfeee..9be2b52831 100644
--- a/src/intel/compiler/brw_reg.h
+++ b/src/intel/compiler/brw_reg.h
@@ -47,6 +47,7 @@
 #include "main/macros.h"
 #include "program/prog_instruction.h"
 #include "brw_eu_defines.h"
+#include "brw_reg_type.h"
 
 #ifdef __cplusplus
 extern "C" {
@@ -202,40 +203,6 @@ brw_mask_for_swizzle(unsigned swz)
    return brw_apply_inv_swizzle_to_mask(swz, ~0);
 }
 
-enum PACKED brw_reg_type {
-   /** Floating-point types: @{ */
-   BRW_REGISTER_TYPE_DF,
-   BRW_REGISTER_TYPE_F,
-   BRW_REGISTER_TYPE_HF,
-   BRW_REGISTER_TYPE_VF,
-   /** @} */
-
-   /** Integer types: @{ */
-   BRW_REGISTER_TYPE_Q,
-   BRW_REGISTER_TYPE_UQ,
-   BRW_REGISTER_TYPE_D,
-   BRW_REGISTER_TYPE_UD,
-   BRW_REGISTER_TYPE_W,
-   BRW_REGISTER_TYPE_UW,
-   BRW_REGISTER_TYPE_B,
-   BRW_REGISTER_TYPE_UB,
-   BRW_REGISTER_TYPE_V,
-   BRW_REGISTER_TYPE_UV,
-   /** @} */
-
-   BRW_REGISTER_TYPE_LAST = BRW_REGISTER_TYPE_UV
-};
-
-unsigned brw_reg_type_to_hw_type(const struct gen_device_info *devinfo,
-                                 enum brw_reg_file file, enum brw_reg_type type);
-
-#define brw_element_size(devinfo, inst, operand)                             \
-   brw_hw_reg_type_to_size(devinfo,                                          \
-                           brw_inst_ ## operand ## _reg_file(devinfo, inst), \
-                           brw_inst_ ## operand ## _reg_type(devinfo, inst))
-unsigned brw_hw_reg_type_to_size(const struct gen_device_info *devinfo,
-                                 enum brw_reg_file file, unsigned type);
-
 const char *brw_reg_type_letters(unsigned brw_reg_type);
 uint32_t brw_swizzle_immediate(enum brw_reg_type type, uint32_t x, unsigned swz);
 
diff --git a/src/intel/compiler/brw_reg_type.c b/src/intel/compiler/brw_reg_type.c
new file mode 100644
index 0000000000..8aac0ca009
--- /dev/null
+++ b/src/intel/compiler/brw_reg_type.c
@@ -0,0 +1,128 @@
+/*
+ * Copyright © 2017 Intel Corporation
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
+ */
+
+#include "brw_reg.h"
+#include "brw_eu_defines.h"
+#include "common/gen_device_info.h"
+
+/**
+ * Convert a brw_reg_type enumeration value into the hardware representation.
+ *
+ * The hardware encoding may depend on whether the value is an immediate.
+ */
+unsigned
+brw_reg_type_to_hw_type(const struct gen_device_info *devinfo,
+                        enum brw_reg_file file,
+                        enum brw_reg_type type)
+{
+   if (file == BRW_IMMEDIATE_VALUE) {
+      static const enum hw_imm_type hw_types[] = {
+         [0 ... BRW_REGISTER_TYPE_LAST] = -1,
+         [BRW_REGISTER_TYPE_UD] = BRW_HW_IMM_TYPE_UD,
+         [BRW_REGISTER_TYPE_D]  = BRW_HW_IMM_TYPE_D,
+         [BRW_REGISTER_TYPE_UW] = BRW_HW_IMM_TYPE_UW,
+         [BRW_REGISTER_TYPE_W]  = BRW_HW_IMM_TYPE_W,
+         [BRW_REGISTER_TYPE_F]  = BRW_HW_IMM_TYPE_F,
+         [BRW_REGISTER_TYPE_UV] = BRW_HW_IMM_TYPE_UV,
+         [BRW_REGISTER_TYPE_VF] = BRW_HW_IMM_TYPE_VF,
+         [BRW_REGISTER_TYPE_V]  = BRW_HW_IMM_TYPE_V,
+         [BRW_REGISTER_TYPE_DF] = GEN8_HW_IMM_TYPE_DF,
+         [BRW_REGISTER_TYPE_HF] = GEN8_HW_IMM_TYPE_HF,
+         [BRW_REGISTER_TYPE_UQ] = GEN8_HW_IMM_TYPE_UQ,
+         [BRW_REGISTER_TYPE_Q]  = GEN8_HW_IMM_TYPE_Q,
+      };
+      assert(type < ARRAY_SIZE(hw_types));
+      assert(hw_types[type] != -1);
+      return hw_types[type];
+   } else {
+      /* Non-immediate registers */
+      static const enum hw_reg_type hw_types[] = {
+         [0 ... BRW_REGISTER_TYPE_LAST] = -1,
+         [BRW_REGISTER_TYPE_UD] = BRW_HW_REG_TYPE_UD,
+         [BRW_REGISTER_TYPE_D]  = BRW_HW_REG_TYPE_D,
+         [BRW_REGISTER_TYPE_UW] = BRW_HW_REG_TYPE_UW,
+         [BRW_REGISTER_TYPE_W]  = BRW_HW_REG_TYPE_W,
+         [BRW_REGISTER_TYPE_UB] = BRW_HW_REG_TYPE_UB,
+         [BRW_REGISTER_TYPE_B]  = BRW_HW_REG_TYPE_B,
+         [BRW_REGISTER_TYPE_F]  = BRW_HW_REG_TYPE_F,
+         [BRW_REGISTER_TYPE_DF] = GEN7_HW_REG_TYPE_DF,
+         [BRW_REGISTER_TYPE_HF] = GEN8_HW_REG_TYPE_HF,
+         [BRW_REGISTER_TYPE_UQ] = GEN8_HW_REG_TYPE_UQ,
+         [BRW_REGISTER_TYPE_Q]  = GEN8_HW_REG_TYPE_Q,
+      };
+      assert(type < ARRAY_SIZE(hw_types));
+      assert(hw_types[type] != -1);
+      return hw_types[type];
+   }
+}
+
+/**
+ * Return the element size given a hardware register type and file.
+ *
+ * The hardware encoding may depend on whether the value is an immediate.
+ */
+unsigned
+brw_hw_reg_type_to_size(const struct gen_device_info *devinfo,
+                        enum brw_reg_file file,
+                        unsigned hw_type)
+{
+   if (file == BRW_IMMEDIATE_VALUE) {
+      static const int hw_sizes[] = {
+         [0 ... 15]            = -1,
+         [BRW_HW_IMM_TYPE_UD]  = 4,
+         [BRW_HW_IMM_TYPE_D]   = 4,
+         [BRW_HW_IMM_TYPE_UW]  = 2,
+         [BRW_HW_IMM_TYPE_W]   = 2,
+         [BRW_HW_IMM_TYPE_UV]  = 2,
+         [BRW_HW_IMM_TYPE_VF]  = 4,
+         [BRW_HW_IMM_TYPE_V]   = 2,
+         [BRW_HW_IMM_TYPE_F]   = 4,
+         [GEN8_HW_IMM_TYPE_UQ] = 8,
+         [GEN8_HW_IMM_TYPE_Q]  = 8,
+         [GEN8_HW_IMM_TYPE_DF] = 8,
+         [GEN8_HW_IMM_TYPE_HF] = 2,
+      };
+      assert(hw_type < ARRAY_SIZE(hw_sizes));
+      assert(hw_sizes[hw_type] != -1);
+      return hw_sizes[hw_type];
+   } else {
+      /* Non-immediate registers */
+      static const int hw_sizes[] = {
+         [0 ... 15]            = -1,
+         [BRW_HW_REG_TYPE_UD]  = 4,
+         [BRW_HW_REG_TYPE_D]   = 4,
+         [BRW_HW_REG_TYPE_UW]  = 2,
+         [BRW_HW_REG_TYPE_W]   = 2,
+         [BRW_HW_REG_TYPE_UB]  = 1,
+         [BRW_HW_REG_TYPE_B]   = 1,
+         [GEN7_HW_REG_TYPE_DF] = 8,
+         [BRW_HW_REG_TYPE_F]   = 4,
+         [GEN8_HW_REG_TYPE_UQ] = 8,
+         [GEN8_HW_REG_TYPE_Q]  = 8,
+         [GEN8_HW_REG_TYPE_HF] = 2,
+      };
+      assert(hw_type < ARRAY_SIZE(hw_sizes));
+      assert(hw_sizes[hw_type] != -1);
+      return hw_sizes[hw_type];
+   }
+}
diff --git a/src/intel/compiler/brw_reg_type.h b/src/intel/compiler/brw_reg_type.h
new file mode 100644
index 0000000000..54262af1fc
--- /dev/null
+++ b/src/intel/compiler/brw_reg_type.h
@@ -0,0 +1,74 @@
+/*
+ * Copyright © 2017 Intel Corporation
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
+ */
+
+#ifndef BRW_REG_TYPE_H
+#define BRW_REG_TYPE_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+enum brw_reg_file;
+struct gen_device_info;
+
+enum PACKED brw_reg_type {
+   /** Floating-point types: @{ */
+   BRW_REGISTER_TYPE_DF,
+   BRW_REGISTER_TYPE_F,
+   BRW_REGISTER_TYPE_HF,
+   BRW_REGISTER_TYPE_VF,
+   /** @} */
+
+   /** Integer types: @{ */
+   BRW_REGISTER_TYPE_Q,
+   BRW_REGISTER_TYPE_UQ,
+   BRW_REGISTER_TYPE_D,
+   BRW_REGISTER_TYPE_UD,
+   BRW_REGISTER_TYPE_W,
+   BRW_REGISTER_TYPE_UW,
+   BRW_REGISTER_TYPE_B,
+   BRW_REGISTER_TYPE_UB,
+   BRW_REGISTER_TYPE_V,
+   BRW_REGISTER_TYPE_UV,
+   /** @} */
+
+   BRW_REGISTER_TYPE_LAST = BRW_REGISTER_TYPE_UV
+};
+
+unsigned
+brw_reg_type_to_hw_type(const struct gen_device_info *devinfo,
+                        enum brw_reg_file file, enum brw_reg_type type);
+
+#define brw_element_size(devinfo, inst, operand)                             \
+   brw_hw_reg_type_to_size(devinfo,                                          \
+                           brw_inst_ ## operand ## _reg_file(devinfo, inst), \
+                           brw_inst_ ## operand ## _reg_type(devinfo, inst))
+unsigned
+brw_hw_reg_type_to_size(const struct gen_device_info *devinfo,
+                        enum brw_reg_file file, unsigned hw_type);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
-- 
2.13.0



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