[Mesa-dev] [PATCH 05/11] radeonsi: add and use si_pm4_state_enabled_and_changed

[Marek Olšák]

From: Marek Olšák <marek.olsak at amd.com>

---
 src/gallium/drivers/radeonsi/si_cp_dma.c        | 20 +++++++++-----------
 src/gallium/drivers/radeonsi/si_state.h         |  3 +++
 src/gallium/drivers/radeonsi/si_state_shaders.c | 12 ++++++------
 3 files changed, 18 insertions(+), 17 deletions(-)

diff --git a/src/gallium/drivers/radeonsi/si_cp_dma.c b/src/gallium/drivers/radeonsi/si_cp_dma.c
index 9f0e506..24fa6fd 100644
--- a/src/gallium/drivers/radeonsi/si_cp_dma.c
+++ b/src/gallium/drivers/radeonsi/si_cp_dma.c
@@ -435,49 +435,47 @@ void cik_prefetch_TC_L2_async(struct si_context *sctx, struct pipe_resource *buf
 			      uint64_t offset, unsigned size)
 {
 	assert(sctx->b.chip_class >= CIK);
 
 	si_copy_buffer(sctx, buf, buf, offset, offset, size, SI_CPDMA_SKIP_ALL);
 }
 
 static void cik_prefetch_shader_async(struct si_context *sctx,
 				      struct si_pm4_state *state)
 {
-	if (state) {
-		struct pipe_resource *bo = &state->bo[0]->b.b;
-		assert(state->nbo == 1);
+	struct pipe_resource *bo = &state->bo[0]->b.b;
+	assert(state->nbo == 1);
 
-		cik_prefetch_TC_L2_async(sctx, bo, 0, bo->width0);
-	}
+	cik_prefetch_TC_L2_async(sctx, bo, 0, bo->width0);
 }
 
 void cik_emit_prefetch_L2(struct si_context *sctx)
 {
 	/* Prefetch shaders and VBO descriptors to TC L2. */
-	if (si_pm4_state_changed(sctx, ls))
+	if (si_pm4_state_enabled_and_changed(sctx, ls))
 		cik_prefetch_shader_async(sctx, sctx->queued.named.ls);
-	if (si_pm4_state_changed(sctx, hs))
+	if (si_pm4_state_enabled_and_changed(sctx, hs))
 		cik_prefetch_shader_async(sctx, sctx->queued.named.hs);
-	if (si_pm4_state_changed(sctx, es))
+	if (si_pm4_state_enabled_and_changed(sctx, es))
 		cik_prefetch_shader_async(sctx, sctx->queued.named.es);
-	if (si_pm4_state_changed(sctx, gs))
+	if (si_pm4_state_enabled_and_changed(sctx, gs))
 		cik_prefetch_shader_async(sctx, sctx->queued.named.gs);
-	if (si_pm4_state_changed(sctx, vs))
+	if (si_pm4_state_enabled_and_changed(sctx, vs))
 		cik_prefetch_shader_async(sctx, sctx->queued.named.vs);
 
 	/* Vertex buffer descriptors are uploaded uncached, so prefetch
 	 * them right after the VS binary. */
 	if (sctx->vertex_buffer_pointer_dirty) {
 		cik_prefetch_TC_L2_async(sctx, &sctx->vertex_buffers.buffer->b.b,
 					 sctx->vertex_buffers.buffer_offset,
 					 sctx->vertex_elements->desc_list_byte_size);
 	}
-	if (si_pm4_state_changed(sctx, ps))
+	if (si_pm4_state_enabled_and_changed(sctx, ps))
 		cik_prefetch_shader_async(sctx, sctx->queued.named.ps);
 
 	sctx->prefetch_L2 = false;
 }
 
 void si_init_cp_dma_functions(struct si_context *sctx)
 {
 	sctx->b.clear_buffer = si_clear_buffer;
 }
diff --git a/src/gallium/drivers/radeonsi/si_state.h b/src/gallium/drivers/radeonsi/si_state.h
index 9fbede7..48e88af 100644
--- a/src/gallium/drivers/radeonsi/si_state.h
+++ b/src/gallium/drivers/radeonsi/si_state.h
@@ -281,20 +281,23 @@ struct si_buffer_resources {
 	/* The i-th bit is set if that element is enabled (non-NULL resource). */
 	unsigned			enabled_mask;
 };
 
 #define si_pm4_block_idx(member) \
 	(offsetof(union si_state, named.member) / sizeof(struct si_pm4_state *))
 
 #define si_pm4_state_changed(sctx, member) \
 	((sctx)->queued.named.member != (sctx)->emitted.named.member)
 
+#define si_pm4_state_enabled_and_changed(sctx, member) \
+	((sctx)->queued.named.member && si_pm4_state_changed(sctx, member))
+
 #define si_pm4_bind_state(sctx, member, value) \
 	do { \
 		(sctx)->queued.named.member = (value); \
 		(sctx)->dirty_states |= 1 << si_pm4_block_idx(member); \
 	} while(0)
 
 #define si_pm4_delete_state(sctx, member, value) \
 	do { \
 		if ((sctx)->queued.named.member == (value)) { \
 			(sctx)->queued.named.member = NULL; \
diff --git a/src/gallium/drivers/radeonsi/si_state_shaders.c b/src/gallium/drivers/radeonsi/si_state_shaders.c
index 0dd6402..cb5a23e 100644
--- a/src/gallium/drivers/radeonsi/si_state_shaders.c
+++ b/src/gallium/drivers/radeonsi/si_state_shaders.c
@@ -3290,26 +3290,26 @@ bool si_update_shaders(struct si_context *sctx)
 			si_mark_atom_dirty(sctx, &sctx->msaa_config);
 
 			if (sctx->b.chip_class == SI)
 				si_mark_atom_dirty(sctx, &sctx->db_render_state);
 
 			if (sctx->framebuffer.nr_samples <= 1)
 				si_mark_atom_dirty(sctx, &sctx->msaa_sample_locs.atom);
 		}
 	}
 
-	if (si_pm4_state_changed(sctx, ls) ||
-	    si_pm4_state_changed(sctx, hs) ||
-	    si_pm4_state_changed(sctx, es) ||
-	    si_pm4_state_changed(sctx, gs) ||
-	    si_pm4_state_changed(sctx, vs) ||
-	    si_pm4_state_changed(sctx, ps)) {
+	if (si_pm4_state_enabled_and_changed(sctx, ls) ||
+	    si_pm4_state_enabled_and_changed(sctx, hs) ||
+	    si_pm4_state_enabled_and_changed(sctx, es) ||
+	    si_pm4_state_enabled_and_changed(sctx, gs) ||
+	    si_pm4_state_enabled_and_changed(sctx, vs) ||
+	    si_pm4_state_enabled_and_changed(sctx, ps)) {
 		if (!si_update_spi_tmpring_size(sctx))
 			return false;
 	}
 
 	if (sctx->b.chip_class >= CIK)
 		sctx->prefetch_L2 = true;
 
 	sctx->do_update_shaders = false;
 	return true;
 }
-- 
2.7.4