[Mesa-dev] [PATCH] i965: Drop uniform buffer alignment back to 16 on Gen6.
kenneth at whitecape.org
Tue Aug 8 18:35:05 UTC 2017
On Tuesday, August 8, 2017 12:26:41 AM PDT Kenneth Graunke wrote:
> We don't push UBOs on Gen6 currently, so there's no need for the
> larger alignment value.
> Cc: "17.2" <mesa-stable at lists.freedesktop.org>
> src/mesa/drivers/dri/i965/brw_context.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
> diff --git a/src/mesa/drivers/dri/i965/brw_context.c b/src/mesa/drivers/dri/i965/brw_context.c
> index 60b14571ed0..9c4e91fe3cd 100644
> --- a/src/mesa/drivers/dri/i965/brw_context.c
> +++ b/src/mesa/drivers/dri/i965/brw_context.c
> @@ -616,7 +616,7 @@ brw_initialize_context_constants(struct brw_context *brw)
> * In order to push UBO data, 3DSTATE_CONSTANT_XS imposes an additional
> * restriction: the start of the buffer needs to be 32B aligned.
> - ctx->Const.UniformBufferOffsetAlignment = 32;
> + ctx->Const.UniformBufferOffsetAlignment = brw->gen >= 7 ? 32 : 16;
> /* ShaderStorageBufferOffsetAlignment should be a cacheline (64 bytes) so
> * that we can safely have the CPU and GPU writing the same SSBO on
Ilia made a good point on IRC - making this different across generations
would make it impossible to take an apitrace on Sandybridge and replay it
on anything newer. That's not a deal breaker, but it's kind of a bummer.
NVIDIA apparently requires an alignment of 256, so 32 should be fine.
I'll just drop this patch unless someone thinks this is a good idea.
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