[Mesa-dev] [PATCH 10/25] i965: Use separate enums for register vs immediate types

[Matt Turner]

On Tue, Aug 8, 2017 at 4:25 PM, Scott D Phillips
<scott.d.phillips at intel.com> wrote:
>> +         [BRW_HW_IMM_TYPE_UV]  = 2,
>> +         [BRW_HW_IMM_TYPE_VF]  = 4,
>> +         [BRW_HW_IMM_TYPE_V]   = 2,
>
> Is this right? I see it was there before, and perhaps I'm being dense,
> but it seems like V and UV should be size 4 from the PRM.

Yes. The encoded immediates themselves are 4 bytes, but this table
captures the size of the individual components once expanded. That's
admittedly a little weird.

A V/UV immediate consists of 8x 4-bit integer values. A restriction
documented in "Gen Graphics » BSpec » 3D and Compute Engine » 3D and
GPGPU Programs » EU Overview » Registers and Register Regions »
Immediate" states "When an immediate vector is used in an instruction,
the destination must be 128-bit aligned with destination horizontal
stride equivalent to a word for an immediate integer vector (v) and
equivalent to a DWord for an immediate float vector (vf).".

So we consider the individual components of the V/UV immediate to
really be words, of size 2.

Thanks for the good question!