[Mesa-dev] [PATCH 0/4] radeonsi: CE odds and ends + gfx9 perf counters

[Nicolai Hähnle]

Hi all,

the first 3 are a bunch of CE-related changes that I still had flying
around from our experiments. Patches 1+3 are clear improvements, 2 is
a wash with how we're currently using the CE. The idea of our internal
experiments was to try to stop the CE from running so far ahead of the
DE by adding a wait packet between the WRITE_CONST_RAM and the
DUMP_CONST_RAM, and so use the CE as a way to prime the L2 cache for
shaders. This didn't really pan out, which is why Marek sent the patch
to disable the CE by default.

Also, the last patch enables performance counters on gfx9. Caveat
emptor: there are of course performance counter changes from VI (as
usual between generations), and it turns out that at least for CPG,
the enums weren't updated properly in line with the hardware changes.
So be sure to double-check/sanity-check whatever you do with performance
counters, but you need to do that anyway. I guess the hardware engineers
just really like keeping us on our toes ;)

Please review!
Cheers,
Nicolai
--
 src/gallium/drivers/radeonsi/si_compute.c    |  2 -
 .../drivers/radeonsi/si_descriptors.c        | 69 ++++++++++--------
 .../drivers/radeonsi/si_perfcounter.c        | 29 +++++++-
 src/gallium/drivers/radeonsi/si_state.h      |  1 -
 src/gallium/drivers/radeonsi/si_state_draw.c | 10 ---
 5 files changed, 67 insertions(+), 44 deletions(-)