[Mesa-dev] [PATCH 17/20] radeon/uvd: add YUYV format support for target buffer

Leo Liu leo.liu at amd.com
Thu Aug 17 10:27:06 UTC 2017



On 08/17/2017 05:15 AM, Christian K├Ânig wrote:
> Am 16.08.2017 um 19:53 schrieb Leo Liu:
>> YUYV is a packed YUV format, and there is no chorma plane
>>
>> v2: add stream type check for YUYV pitch setup
>>
>> Signed-off-by: Leo Liu <leo.liu at amd.com>
>> ---
>>   src/gallium/drivers/radeon/radeon_uvd.c | 8 ++++++--
>>   src/gallium/drivers/radeonsi/si_uvd.c   | 2 +-
>>   2 files changed, 7 insertions(+), 3 deletions(-)
>>
>> diff --git a/src/gallium/drivers/radeon/radeon_uvd.c 
>> b/src/gallium/drivers/radeon/radeon_uvd.c
>> index b6106c6e1f..e809e24405 100644
>> --- a/src/gallium/drivers/radeon/radeon_uvd.c
>> +++ b/src/gallium/drivers/radeon/radeon_uvd.c
>> @@ -1547,6 +1547,8 @@ void ruvd_set_dt_surfaces(struct ruvd_msg *msg, 
>> struct radeon_surf *luma,
>>       default:
>>       case RUVD_SURFACE_TYPE_LEGACY:
>>           msg->body.decode.dt_pitch = luma->u.legacy.level[0].nblk_x;
>> +        if (msg->body.decode.stream_type == RUVD_CODEC_MJPEG && 
>> !chroma)
>> +            msg->body.decode.dt_pitch *= 2;
>
> That still doesn't look correct to me. Please try the following instead:
>
> msg->body.decode.dt_pitch = luma->u.legacy.level[0].nblk_x * luma->bpe;
>
> Does that work as well?

I think it works. I tried that in the very beginning, but I have to 
double check when back to the office later.

There was a patch back to March "radeon/UVD: fix the decoding target 
pitch calculation" removed "bpe" for normal NV12 format.

so I think for this YUYV, we still need condition, and code will be like

if (msg->body.decode.stream_type == RUVD_CODEC_MJPEG && !chroma)
    msg->body.decode.dt_pitch = luma->u.legacy.level[0].nblk_x * luma->bpe;


Other than that, could you review the patch 1 v2 ? that's the only one 
left not reviewed in the series after this "pitch" one.

Thanks,
Leo

>
> Christian.
>
>>           switch (luma->u.legacy.level[0].mode) {
>>           case RADEON_SURF_MODE_LINEAR_ALIGNED:
>>               msg->body.decode.dt_tiling_mode = RUVD_TILE_LINEAR;
>> @@ -1566,10 +1568,12 @@ void ruvd_set_dt_surfaces(struct ruvd_msg 
>> *msg, struct radeon_surf *luma,
>>           }
>>             msg->body.decode.dt_luma_top_offset = 
>> texture_offset(luma, 0, type);
>> -        msg->body.decode.dt_chroma_top_offset = 
>> texture_offset(chroma, 0, type);
>> +        if (chroma)
>> +            msg->body.decode.dt_chroma_top_offset = 
>> texture_offset(chroma, 0, type);
>>           if (msg->body.decode.dt_field_mode) {
>>               msg->body.decode.dt_luma_bottom_offset = 
>> texture_offset(luma, 1, type);
>> -            msg->body.decode.dt_chroma_bottom_offset = 
>> texture_offset(chroma, 1, type);
>> +            if (chroma)
>> +                msg->body.decode.dt_chroma_bottom_offset = 
>> texture_offset(chroma, 1, type);
>>           } else {
>>               msg->body.decode.dt_luma_bottom_offset = 
>> msg->body.decode.dt_luma_top_offset;
>>               msg->body.decode.dt_chroma_bottom_offset = 
>> msg->body.decode.dt_chroma_top_offset;
>> diff --git a/src/gallium/drivers/radeonsi/si_uvd.c 
>> b/src/gallium/drivers/radeonsi/si_uvd.c
>> index d17a6656a4..2441ad248c 100644
>> --- a/src/gallium/drivers/radeonsi/si_uvd.c
>> +++ b/src/gallium/drivers/radeonsi/si_uvd.c
>> @@ -131,7 +131,7 @@ static struct pb_buffer* si_uvd_set_dtb(struct 
>> ruvd_msg *msg, struct vl_video_bu
>>         msg->body.decode.dt_field_mode = buf->base.interlaced;
>>   -    ruvd_set_dt_surfaces(msg, &luma->surface, &chroma->surface, 
>> type);
>> +    ruvd_set_dt_surfaces(msg, &luma->surface, (chroma) ? 
>> &chroma->surface : NULL, type);
>>         return luma->resource.buf;
>>   }
>
>



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