[Mesa-dev] [PATCH 10/27] i965: Add shader cache support for compute
Jordan Justen
jordan.l.justen at intel.com
Sat Aug 19 07:44:26 UTC 2017
Signed-off-by: Jordan Justen <jordan.l.justen at intel.com>
---
src/mesa/drivers/dri/i965/brw_cs.c | 25 ++++++++++++-------
src/mesa/drivers/dri/i965/brw_cs.h | 3 +++
src/mesa/drivers/dri/i965/brw_disk_cache.c | 36 +++++++++++++++++++++++++++-
src/mesa/drivers/dri/i965/brw_state.h | 3 ++-
src/mesa/drivers/dri/i965/brw_state_upload.c | 3 ++-
5 files changed, 58 insertions(+), 12 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_cs.c b/src/mesa/drivers/dri/i965/brw_cs.c
index f8aee239a8..2f3e5fd3fd 100644
--- a/src/mesa/drivers/dri/i965/brw_cs.c
+++ b/src/mesa/drivers/dri/i965/brw_cs.c
@@ -174,7 +174,7 @@ brw_codegen_cs_prog(struct brw_context *brw,
}
-static void
+void
brw_cs_populate_key(struct brw_context *brw, struct brw_cs_prog_key *key)
{
struct gl_context *ctx = &brw->ctx;
@@ -210,14 +210,21 @@ brw_upload_cs_prog(struct brw_context *brw)
brw_cs_populate_key(brw, &key);
- if (!brw_search_cache(&brw->cache, BRW_CACHE_CS_PROG,
- &key, sizeof(key),
- &brw->cs.base.prog_offset,
- &brw->cs.base.prog_data)) {
- bool success = brw_codegen_cs_prog(brw, cp, &key);
- (void) success;
- assert(success);
- }
+ if (brw_search_cache(&brw->cache, BRW_CACHE_CS_PROG,
+ &key, sizeof(key),
+ &brw->cs.base.prog_offset,
+ &brw->cs.base.prog_data))
+ return;
+
+ if (brw_disk_cache_upload_program(brw, MESA_SHADER_COMPUTE))
+ return;
+
+ cp = (struct brw_program *) brw->compute_program;
+ cp->id = key.program_string_id;
+
+ bool success = brw_codegen_cs_prog(brw, cp, &key);
+ (void) success;
+ assert(success);
}
diff --git a/src/mesa/drivers/dri/i965/brw_cs.h b/src/mesa/drivers/dri/i965/brw_cs.h
index 890a0c8a80..60eb19c359 100644
--- a/src/mesa/drivers/dri/i965/brw_cs.h
+++ b/src/mesa/drivers/dri/i965/brw_cs.h
@@ -32,6 +32,9 @@ extern "C" {
void
brw_upload_cs_prog(struct brw_context *brw);
+void
+brw_cs_populate_key(struct brw_context *brw, struct brw_cs_prog_key *key);
+
#ifdef __cplusplus
}
#endif
diff --git a/src/mesa/drivers/dri/i965/brw_disk_cache.c b/src/mesa/drivers/dri/i965/brw_disk_cache.c
index cdf2a13a69..e2dba76679 100644
--- a/src/mesa/drivers/dri/i965/brw_disk_cache.c
+++ b/src/mesa/drivers/dri/i965/brw_disk_cache.c
@@ -31,6 +31,7 @@
#include "brw_context.h"
#include "brw_program.h"
+#include "brw_cs.h"
#include "brw_gs.h"
#include "brw_state.h"
#include "brw_vs.h"
@@ -160,6 +161,7 @@ read_and_upload(struct brw_context *brw, struct disk_cache *cache,
struct brw_tes_prog_key tes_key;
struct brw_gs_prog_key gs_key;
struct brw_vs_prog_key vs_key;
+ struct brw_cs_prog_key cs_key;
switch (stage) {
case MESA_SHADER_VERTEX:
@@ -190,6 +192,11 @@ read_and_upload(struct brw_context *brw, struct disk_cache *cache,
wm_key.program_string_id = 0;
gen_shader_sha1(brw, prog, stage, &wm_key, binary_sha1);
break;
+ case MESA_SHADER_COMPUTE:
+ brw_cs_populate_key(brw, &cs_key);
+ cs_key.program_string_id = 0;
+ gen_shader_sha1(brw, prog, stage, &cs_key, binary_sha1);
+ break;
default:
unreachable("Unsupported stage!");
}
@@ -256,6 +263,11 @@ read_and_upload(struct brw_context *brw, struct disk_cache *cache,
SET_UPLOAD_PRAMS(wm, FS, wp)
break;
}
+ case MESA_SHADER_COMPUTE: {
+ struct brw_program *cp = (struct brw_program *) prog;
+ SET_UPLOAD_PRAMS(cs, CS, cp)
+ break;
+ }
default:
unreachable("Unsupported stage!");
}
@@ -395,7 +407,7 @@ write_program_data(struct brw_context *brw, struct gl_program *prog,
}
void
-brw_disk_cache_write_program(struct brw_context *brw)
+brw_disk_cache_write_render_programs(struct brw_context *brw)
{
struct disk_cache *cache = brw->ctx.Cache;
if (cache == NULL)
@@ -467,3 +479,25 @@ brw_disk_cache_write_program(struct brw_context *brw)
MESA_SHADER_FRAGMENT);
}
}
+
+void
+brw_disk_cache_write_compute_program(struct brw_context *brw)
+{
+ struct disk_cache *cache = brw->ctx.Cache;
+ if (cache == NULL)
+ return;
+
+ struct gl_program *prog =
+ brw->ctx._Shader->CurrentProgram[MESA_SHADER_COMPUTE];
+ if (prog && !prog->program_written_to_cache) {
+ struct brw_cs_prog_key cs_key;
+ brw_cs_populate_key(brw, &cs_key);
+ cs_key.program_string_id = 0;
+
+ write_program_data(brw, prog, &cs_key, brw->cs.base.prog_data,
+ brw->cs.base.prog_data->program_size,
+ sizeof(struct brw_cs_prog_data),
+ brw->cs.base.prog_offset, cache,
+ MESA_SHADER_COMPUTE);
+ }
+}
diff --git a/src/mesa/drivers/dri/i965/brw_state.h b/src/mesa/drivers/dri/i965/brw_state.h
index 8b468c752c..ff8f1b5157 100644
--- a/src/mesa/drivers/dri/i965/brw_state.h
+++ b/src/mesa/drivers/dri/i965/brw_state.h
@@ -134,7 +134,8 @@ void gen8_write_pma_stall_bits(struct brw_context *brw,
/* brw_disk_cache.c */
bool brw_disk_cache_upload_program(struct brw_context *brw,
gl_shader_stage stage);
-void brw_disk_cache_write_program(struct brw_context *brw);
+void brw_disk_cache_write_compute_program(struct brw_context *brw);
+void brw_disk_cache_write_render_programs(struct brw_context *brw);
/***********************************************************************
* brw_state.c
diff --git a/src/mesa/drivers/dri/i965/brw_state_upload.c b/src/mesa/drivers/dri/i965/brw_state_upload.c
index 140146970b..4d4cd6bf38 100644
--- a/src/mesa/drivers/dri/i965/brw_state_upload.c
+++ b/src/mesa/drivers/dri/i965/brw_state_upload.c
@@ -435,9 +435,10 @@ brw_upload_programs(struct brw_context *brw,
brw_upload_sf_prog(brw);
}
- brw_disk_cache_write_program(brw);
+ brw_disk_cache_write_render_programs(brw);
} else if (pipeline == BRW_COMPUTE_PIPELINE) {
brw_upload_cs_prog(brw);
+ brw_disk_cache_write_compute_program(brw);
}
}
--
2.14.0
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