[Mesa-dev] [PATCH v4 4/6] radeonsi: add si_emit_global_shader_pointers() helper

[Samuel Pitoiset]

To share common code between rw buffers and bindless descriptors.

v3: - rename to si_emit_global_shader_pointers()

Signed-off-by: Samuel Pitoiset <samuel.pitoiset at gmail.com>
Reviewed-by: Marek Olšák <marek.olsak at amd.com> (v3)
---
 src/gallium/drivers/radeonsi/si_descriptors.c | 57 +++++++++++++++------------
 1 file changed, 31 insertions(+), 26 deletions(-)

diff --git a/src/gallium/drivers/radeonsi/si_descriptors.c b/src/gallium/drivers/radeonsi/si_descriptors.c
index 45e31c5c6b..eef9d7cd1c 100644
--- a/src/gallium/drivers/radeonsi/si_descriptors.c
+++ b/src/gallium/drivers/radeonsi/si_descriptors.c
@@ -2195,6 +2195,35 @@ static void si_emit_shader_pointer(struct si_context *sctx,
 	radeon_emit(cs, va >> 32);
 }
 
+static void si_emit_global_shader_pointers(struct si_context *sctx,
+					   struct si_descriptors *descs)
+{
+	si_emit_shader_pointer(sctx, descs,
+			       R_00B030_SPI_SHADER_USER_DATA_PS_0);
+	si_emit_shader_pointer(sctx, descs,
+			       R_00B130_SPI_SHADER_USER_DATA_VS_0);
+
+	if (sctx->b.chip_class >= GFX9) {
+		/* GFX9 merged LS-HS and ES-GS.
+		 * Set RW_BUFFERS in the special registers, so that
+		 * it's preloaded into s[0:1] instead of s[8:9].
+		 */
+		si_emit_shader_pointer(sctx, descs,
+				       R_00B208_SPI_SHADER_USER_DATA_ADDR_LO_GS);
+		si_emit_shader_pointer(sctx, descs,
+				       R_00B408_SPI_SHADER_USER_DATA_ADDR_LO_HS);
+	} else {
+		si_emit_shader_pointer(sctx, descs,
+				       R_00B230_SPI_SHADER_USER_DATA_GS_0);
+		si_emit_shader_pointer(sctx, descs,
+				       R_00B330_SPI_SHADER_USER_DATA_ES_0);
+		si_emit_shader_pointer(sctx, descs,
+				       R_00B430_SPI_SHADER_USER_DATA_HS_0);
+		si_emit_shader_pointer(sctx, descs,
+				       R_00B530_SPI_SHADER_USER_DATA_LS_0);
+	}
+}
+
 void si_emit_graphics_shader_pointers(struct si_context *sctx,
                                       struct r600_atom *atom)
 {
@@ -2204,32 +2233,8 @@ void si_emit_graphics_shader_pointers(struct si_context *sctx,
 
 	descs = &sctx->descriptors[SI_DESCS_RW_BUFFERS];
 
-	if (sctx->shader_pointers_dirty & (1 << SI_DESCS_RW_BUFFERS)) {
-		si_emit_shader_pointer(sctx, descs,
-				       R_00B030_SPI_SHADER_USER_DATA_PS_0);
-		si_emit_shader_pointer(sctx, descs,
-				       R_00B130_SPI_SHADER_USER_DATA_VS_0);
-
-		if (sctx->b.chip_class >= GFX9) {
-			/* GFX9 merged LS-HS and ES-GS.
-			 * Set RW_BUFFERS in the special registers, so that
-			 * it's preloaded into s[0:1] instead of s[8:9].
-			 */
-			si_emit_shader_pointer(sctx, descs,
-					       R_00B208_SPI_SHADER_USER_DATA_ADDR_LO_GS);
-			si_emit_shader_pointer(sctx, descs,
-					       R_00B408_SPI_SHADER_USER_DATA_ADDR_LO_HS);
-		} else {
-			si_emit_shader_pointer(sctx, descs,
-					       R_00B230_SPI_SHADER_USER_DATA_GS_0);
-			si_emit_shader_pointer(sctx, descs,
-					       R_00B330_SPI_SHADER_USER_DATA_ES_0);
-			si_emit_shader_pointer(sctx, descs,
-					       R_00B430_SPI_SHADER_USER_DATA_HS_0);
-			si_emit_shader_pointer(sctx, descs,
-					       R_00B530_SPI_SHADER_USER_DATA_LS_0);
-		}
-	}
+	if (sctx->shader_pointers_dirty & (1 << SI_DESCS_RW_BUFFERS))
+		si_emit_global_shader_pointers(sctx, descs);
 
 	mask = sctx->shader_pointers_dirty &
 	       u_bit_consecutive(SI_DESCS_FIRST_SHADER,
-- 
2.14.1