[Mesa-dev] [PATCH 16/47] glsl: Add "built-in" functions to do trunc(fp64)
Elie Tournier
tournier.elie at gmail.com
Wed Aug 23 11:07:46 UTC 2017
Signed-off-by: Elie Tournier <elie.tournier at collabora.com>
---
src/compiler/glsl/builtin_float64.h | 121 ++++++++++++++++++++++++++++++++
src/compiler/glsl/builtin_functions.cpp | 4 ++
src/compiler/glsl/builtin_functions.h | 3 +
src/compiler/glsl/float64.glsl | 23 ++++++
src/compiler/glsl/glcpp/glcpp-parse.y | 1 +
5 files changed, 152 insertions(+)
diff --git a/src/compiler/glsl/builtin_float64.h b/src/compiler/glsl/builtin_float64.h
index b16bc5def5..2bce013d0e 100644
--- a/src/compiler/glsl/builtin_float64.h
+++ b/src/compiler/glsl/builtin_float64.h
@@ -18133,3 +18133,124 @@ fsqrt64(void *mem_ctx, builtin_available_predicate avail)
sig->replace_parameters(&sig_parameters);
return sig;
}
+ir_function_signature *
+ftrunc64(void *mem_ctx, builtin_available_predicate avail)
+{
+ ir_function_signature *const sig =
+ new(mem_ctx) ir_function_signature(glsl_type::uvec2_type, avail);
+ ir_factory body(&sig->body, mem_ctx);
+ sig->is_defined = true;
+
+ exec_list sig_parameters;
+
+ ir_variable *const r0F09 = new(mem_ctx) ir_variable(glsl_type::uvec2_type, "a", ir_var_function_in);
+ sig_parameters.push_tail(r0F09);
+ ir_variable *const r0F0A = body.make_temp(glsl_type::uvec2_type, "return_value");
+ ir_variable *const r0F0B = body.make_temp(glsl_type::int_type, "assignment_tmp");
+ ir_expression *const r0F0C = rshift(swizzle_y(r0F09), body.constant(int(20)));
+ ir_expression *const r0F0D = bit_and(r0F0C, body.constant(2047u));
+ ir_expression *const r0F0E = expr(ir_unop_u2i, r0F0D);
+ body.emit(assign(r0F0B, add(r0F0E, body.constant(int(-1023))), 0x01));
+
+ /* IF CONDITION */
+ ir_expression *const r0F10 = less(r0F0B, body.constant(int(0)));
+ ir_if *f0F0F = new(mem_ctx) ir_if(operand(r0F10).val);
+ exec_list *const f0F0F_parent_instructions = body.instructions;
+
+ /* THEN INSTRUCTIONS */
+ body.instructions = &f0F0F->then_instructions;
+
+ body.emit(assign(r0F0A, ir_constant::zero(mem_ctx, glsl_type::uvec2_type), 0x03));
+
+
+ /* ELSE INSTRUCTIONS */
+ body.instructions = &f0F0F->else_instructions;
+
+ /* IF CONDITION */
+ ir_expression *const r0F12 = greater(r0F0B, body.constant(int(52)));
+ ir_if *f0F11 = new(mem_ctx) ir_if(operand(r0F12).val);
+ exec_list *const f0F11_parent_instructions = body.instructions;
+
+ /* THEN INSTRUCTIONS */
+ body.instructions = &f0F11->then_instructions;
+
+ body.emit(assign(r0F0A, r0F09, 0x03));
+
+
+ /* ELSE INSTRUCTIONS */
+ body.instructions = &f0F11->else_instructions;
+
+ ir_variable *const r0F13 = body.make_temp(glsl_type::int_type, "assignment_tmp");
+ body.emit(assign(r0F13, sub(body.constant(int(52)), r0F0B), 0x01));
+
+ ir_variable *const r0F14 = body.make_temp(glsl_type::uint_type, "conditional_tmp");
+ /* IF CONDITION */
+ ir_expression *const r0F16 = gequal(r0F13, body.constant(int(32)));
+ ir_if *f0F15 = new(mem_ctx) ir_if(operand(r0F16).val);
+ exec_list *const f0F15_parent_instructions = body.instructions;
+
+ /* THEN INSTRUCTIONS */
+ body.instructions = &f0F15->then_instructions;
+
+ body.emit(assign(r0F14, body.constant(0u), 0x01));
+
+
+ /* ELSE INSTRUCTIONS */
+ body.instructions = &f0F15->else_instructions;
+
+ body.emit(assign(r0F14, lshift(body.constant(4294967295u), r0F13), 0x01));
+
+
+ body.instructions = f0F15_parent_instructions;
+ body.emit(f0F15);
+
+ /* END IF */
+
+ ir_variable *const r0F17 = body.make_temp(glsl_type::uint_type, "conditional_tmp");
+ /* IF CONDITION */
+ ir_expression *const r0F19 = less(r0F13, body.constant(int(33)));
+ ir_if *f0F18 = new(mem_ctx) ir_if(operand(r0F19).val);
+ exec_list *const f0F18_parent_instructions = body.instructions;
+
+ /* THEN INSTRUCTIONS */
+ body.instructions = &f0F18->then_instructions;
+
+ body.emit(assign(r0F17, body.constant(4294967295u), 0x01));
+
+
+ /* ELSE INSTRUCTIONS */
+ body.instructions = &f0F18->else_instructions;
+
+ ir_expression *const r0F1A = add(r0F13, body.constant(int(-32)));
+ body.emit(assign(r0F17, lshift(body.constant(4294967295u), r0F1A), 0x01));
+
+
+ body.instructions = f0F18_parent_instructions;
+ body.emit(f0F18);
+
+ /* END IF */
+
+ ir_variable *const r0F1B = body.make_temp(glsl_type::uvec2_type, "vec_ctor");
+ body.emit(assign(r0F1B, bit_and(r0F14, swizzle_x(r0F09)), 0x01));
+
+ body.emit(assign(r0F1B, bit_and(r0F17, swizzle_y(r0F09)), 0x02));
+
+ body.emit(assign(r0F0A, r0F1B, 0x03));
+
+
+ body.instructions = f0F11_parent_instructions;
+ body.emit(f0F11);
+
+ /* END IF */
+
+
+ body.instructions = f0F0F_parent_instructions;
+ body.emit(f0F0F);
+
+ /* END IF */
+
+ body.emit(ret(r0F0A));
+
+ sig->replace_parameters(&sig_parameters);
+ return sig;
+}
diff --git a/src/compiler/glsl/builtin_functions.cpp b/src/compiler/glsl/builtin_functions.cpp
index 48f13af7b2..ca59bf9a0c 100644
--- a/src/compiler/glsl/builtin_functions.cpp
+++ b/src/compiler/glsl/builtin_functions.cpp
@@ -3384,6 +3384,10 @@ builtin_builder::create_builtins()
generate_ir::fsqrt64(mem_ctx, integer_functions_supported),
NULL);
+ add_function("__builtin_ftrunc64",
+ generate_ir::ftrunc64(mem_ctx, integer_functions_supported),
+ NULL);
+
#undef F
#undef FI
#undef FIUD_VEC
diff --git a/src/compiler/glsl/builtin_functions.h b/src/compiler/glsl/builtin_functions.h
index a1d0adbe1f..b98a34ca3e 100644
--- a/src/compiler/glsl/builtin_functions.h
+++ b/src/compiler/glsl/builtin_functions.h
@@ -112,6 +112,9 @@ fp32_to_fp64(void *mem_ctx, builtin_available_predicate avail);
ir_function_signature *
fsqrt64(void *mem_ctx, builtin_available_predicate avail);
+ir_function_signature *
+ftrunc64(void *mem_ctx, builtin_available_predicate avail);
+
}
#endif /* BULITIN_FUNCTIONS_H */
diff --git a/src/compiler/glsl/float64.glsl b/src/compiler/glsl/float64.glsl
index 789d6b62e6..54b0275fbb 100644
--- a/src/compiler/glsl/float64.glsl
+++ b/src/compiler/glsl/float64.glsl
@@ -1418,3 +1418,26 @@ fsqrt64(uvec2 a)
shift64ExtraRightJamming(zFrac0, zFrac1, 0u, 10, zFrac0, zFrac1, zFrac2);
return roundAndPackFloat64(0u, zExp, zFrac0, zFrac1, zFrac2);
}
+
+uvec2
+ftrunc64(uvec2 a)
+{
+ int aExp = extractFloat64Exp(a);
+
+ int unbiasedExp = aExp - 1023;
+
+ if (unbiasedExp < 0)
+ return uvec2(0u, 0u);
+ else if (unbiasedExp > 52)
+ return a;
+ else {
+ uint zLo;
+ uint zHi;
+ int fracBits = 52 - unbiasedExp;
+ uint maskLo = (fracBits >= 32) ? 0u : (~0u << fracBits);
+ uint maskHi = (fracBits < 33) ? ~0u : (~0u << (fracBits - 32));
+ zLo = maskLo & a.x;
+ zHi = maskHi & a.y;
+ return uvec2(zLo, zHi);
+ }
+}
diff --git a/src/compiler/glsl/glcpp/glcpp-parse.y b/src/compiler/glsl/glcpp/glcpp-parse.y
index 41be2f2b65..c7e6464c5a 100644
--- a/src/compiler/glsl/glcpp/glcpp-parse.y
+++ b/src/compiler/glsl/glcpp/glcpp-parse.y
@@ -2464,6 +2464,7 @@ _glcpp_parser_handle_version_declaration(glcpp_parser_t *parser, intmax_t versio
add_builtin_define(parser, "__have_builtin_builtin_fp64_to_fp32", 1);
add_builtin_define(parser, "__have_builtin_builtin_fp32_to_fp64", 1);
add_builtin_define(parser, "__have_builtin_builtin_fsqrt64", 1);
+ add_builtin_define(parser, "__have_builtin_builtin_ftrunc64", 1);
}
}
--
2.14.1
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