[Mesa-dev] [PATCH 36/47] glsl: Add a lowering pass for 64-bit float rcp()
Elie Tournier
tournier.elie at gmail.com
Wed Aug 23 11:08:06 UTC 2017
Signed-off-by: Elie Tournier <elie.tournier at collabora.com>
---
src/compiler/glsl/ir_optimization.h | 1 +
src/compiler/glsl/lower_64bit.cpp | 7 +++++++
src/mesa/state_tracker/st_glsl_to_tgsi.cpp | 3 ++-
3 files changed, 10 insertions(+), 1 deletion(-)
diff --git a/src/compiler/glsl/ir_optimization.h b/src/compiler/glsl/ir_optimization.h
index 4a44ee7660..e18924d62b 100644
--- a/src/compiler/glsl/ir_optimization.h
+++ b/src/compiler/glsl/ir_optimization.h
@@ -77,6 +77,7 @@
#define SQRT64 (1U << 16)
#define TRUNC64 (1U << 17)
#define ROUND64 (1U << 18)
+#define RCP64 (1U << 19)
/**
* \see class lower_packing_builtins_visitor
diff --git a/src/compiler/glsl/lower_64bit.cpp b/src/compiler/glsl/lower_64bit.cpp
index 894503a14f..f8fcf9fd0a 100644
--- a/src/compiler/glsl/lower_64bit.cpp
+++ b/src/compiler/glsl/lower_64bit.cpp
@@ -478,6 +478,13 @@ lower_64bit_visitor::handle_rvalue(ir_rvalue **rvalue)
}
break;
+ case ir_unop_rcp:
+ if (lowering(RCP64)) {
+ if (ir->type->base_type == GLSL_TYPE_DOUBLE)
+ *rvalue = handle_op(ir, "__builtin_frcp64", generate_ir::frcp64);
+ }
+ break;
+
case ir_unop_round_even:
if (lowering(ROUND64)) {
if (ir->type->base_type == GLSL_TYPE_DOUBLE)
diff --git a/src/mesa/state_tracker/st_glsl_to_tgsi.cpp b/src/mesa/state_tracker/st_glsl_to_tgsi.cpp
index 760ffd594e..dc88a881f6 100644
--- a/src/mesa/state_tracker/st_glsl_to_tgsi.cpp
+++ b/src/mesa/state_tracker/st_glsl_to_tgsi.cpp
@@ -7074,7 +7074,8 @@ st_link_shader(struct gl_context *ctx, struct gl_shader_program *prog)
F2D |
SQRT64 |
TRUNC64 |
- ROUND64;
+ ROUND64 |
+ RCP64;
lower_64bit_double_instructions(ir, lower_inst);
}
--
2.14.1
More information about the mesa-dev
mailing list