[Mesa-dev] [PATCH 10/11] radv: Implement multiview draws.

Bas Nieuwenhuizen bas at basnieuwenhuizen.nl
Wed Aug 23 20:51:52 UTC 2017


---
 src/amd/vulkan/radv_cmd_buffer.c | 132 ++++++++++++++++++++++++++++++---------
 src/amd/vulkan/radv_private.h    |   1 +
 2 files changed, 105 insertions(+), 28 deletions(-)

diff --git a/src/amd/vulkan/radv_cmd_buffer.c b/src/amd/vulkan/radv_cmd_buffer.c
index ed11a4aa35e..4960bdf758a 100644
--- a/src/amd/vulkan/radv_cmd_buffer.c
+++ b/src/amd/vulkan/radv_cmd_buffer.c
@@ -2657,6 +2657,28 @@ void radv_CmdNextSubpass(
 	radv_cmd_buffer_clear_subpass(cmd_buffer);
 }
 
+static void radv_emit_view_index(struct radv_cmd_buffer *cmd_buffer, unsigned index)
+{
+	struct radv_pipeline *pipeline = cmd_buffer->state.pipeline;
+	for (unsigned stage = 0; stage < MESA_SHADER_STAGES; ++stage) {
+		if (!pipeline->shaders[stage])
+			continue;
+		struct ac_userdata_info *loc = radv_lookup_user_sgpr(pipeline, stage, AC_UD_VIEW_INDEX);
+		if (loc->sgpr_idx == -1)
+			continue;
+		uint32_t base_reg = radv_shader_stage_to_user_data_0(stage, radv_pipeline_has_gs(pipeline), radv_pipeline_has_tess(pipeline));
+		radeon_set_sh_reg(cmd_buffer->cs, base_reg + loc->sgpr_idx * 4, index);
+
+	}
+	if (pipeline->gs_copy_shader) {
+		struct ac_userdata_info *loc = &pipeline->gs_copy_shader->info.user_sgprs_locs.shader_data[AC_UD_VIEW_INDEX];
+		if (loc->sgpr_idx != -1) {
+			uint32_t base_reg = R_00B130_SPI_SHADER_USER_DATA_VS_0;
+			radeon_set_sh_reg(cmd_buffer->cs, base_reg + loc->sgpr_idx * 4, index);
+		}
+	}
+}
+
 void radv_CmdDraw(
 	VkCommandBuffer                             commandBuffer,
 	uint32_t                                    vertexCount,
@@ -2668,7 +2690,7 @@ void radv_CmdDraw(
 
 	radv_cmd_buffer_flush_state(cmd_buffer, false, (instanceCount > 1), false, vertexCount);
 
-	MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws, cmd_buffer->cs, 10);
+	MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws, cmd_buffer->cs, 12 * MAX_VIEWS);
 
 	assert(cmd_buffer->state.pipeline->graphics.vtx_base_sgpr);
 	radeon_set_sh_reg_seq(cmd_buffer->cs, cmd_buffer->state.pipeline->graphics.vtx_base_sgpr,
@@ -2681,10 +2703,24 @@ void radv_CmdDraw(
 	radeon_emit(cmd_buffer->cs, PKT3(PKT3_NUM_INSTANCES, 0, cmd_buffer->state.predicating));
 	radeon_emit(cmd_buffer->cs, instanceCount);
 
-	radeon_emit(cmd_buffer->cs, PKT3(PKT3_DRAW_INDEX_AUTO, 1, cmd_buffer->state.predicating));
-	radeon_emit(cmd_buffer->cs, vertexCount);
-	radeon_emit(cmd_buffer->cs, V_0287F0_DI_SRC_SEL_AUTO_INDEX |
-		    S_0287F0_USE_OPAQUE(0));
+	if (!cmd_buffer->state.subpass->view_mask) {
+		radeon_emit(cmd_buffer->cs, PKT3(PKT3_DRAW_INDEX_AUTO, 1, cmd_buffer->state.predicating));
+		radeon_emit(cmd_buffer->cs, vertexCount);
+		radeon_emit(cmd_buffer->cs, V_0287F0_DI_SRC_SEL_AUTO_INDEX |
+		                            S_0287F0_USE_OPAQUE(0));
+	} else {
+		for (unsigned i = 0; (1u << i) <= cmd_buffer->state.subpass->view_mask; ++i) {
+			if ((1u << i) & cmd_buffer->state.subpass->view_mask) {
+				radv_emit_view_index(cmd_buffer, i);
+
+				radeon_emit(cmd_buffer->cs, PKT3(PKT3_DRAW_INDEX_AUTO, 1, cmd_buffer->state.predicating));
+				radeon_emit(cmd_buffer->cs, vertexCount);
+				radeon_emit(cmd_buffer->cs, V_0287F0_DI_SRC_SEL_AUTO_INDEX |
+				                            S_0287F0_USE_OPAQUE(0));
+
+			}
+		}
+	}
 
 	assert(cmd_buffer->cs->cdw <= cdw_max);
 
@@ -2705,7 +2741,7 @@ void radv_CmdDrawIndexed(
 
 	radv_cmd_buffer_flush_state(cmd_buffer, true, (instanceCount > 1), false, indexCount);
 
-	MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws, cmd_buffer->cs, 15);
+	MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws, cmd_buffer->cs, 17 * MAX_VIEWS);
 
 	if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9) {
 		radeon_set_uconfig_reg_idx(cmd_buffer->cs, R_03090C_VGT_INDEX_TYPE,
@@ -2728,12 +2764,28 @@ void radv_CmdDrawIndexed(
 
 	index_va = cmd_buffer->state.index_va;
 	index_va += firstIndex * index_size;
-	radeon_emit(cmd_buffer->cs, PKT3(PKT3_DRAW_INDEX_2, 4, false));
-	radeon_emit(cmd_buffer->cs, cmd_buffer->state.max_index_count);
-	radeon_emit(cmd_buffer->cs, index_va);
-	radeon_emit(cmd_buffer->cs, (index_va >> 32UL) & 0xFF);
-	radeon_emit(cmd_buffer->cs, indexCount);
-	radeon_emit(cmd_buffer->cs, V_0287F0_DI_SRC_SEL_DMA);
+	if (!cmd_buffer->state.subpass->view_mask) {
+		radeon_emit(cmd_buffer->cs, PKT3(PKT3_DRAW_INDEX_2, 4, false));
+		radeon_emit(cmd_buffer->cs, cmd_buffer->state.max_index_count);
+		radeon_emit(cmd_buffer->cs, index_va);
+		radeon_emit(cmd_buffer->cs, (index_va >> 32UL) & 0xFF);
+		radeon_emit(cmd_buffer->cs, indexCount);
+		radeon_emit(cmd_buffer->cs, V_0287F0_DI_SRC_SEL_DMA);
+	} else {
+		for (unsigned i = 0; (1u << i) <= cmd_buffer->state.subpass->view_mask; ++i) {
+			if ((1u << i) & cmd_buffer->state.subpass->view_mask) {
+				radv_emit_view_index(cmd_buffer, i);
+
+				radeon_emit(cmd_buffer->cs, PKT3(PKT3_DRAW_INDEX_2, 4, false));
+				radeon_emit(cmd_buffer->cs, cmd_buffer->state.max_index_count);
+				radeon_emit(cmd_buffer->cs, index_va);
+				radeon_emit(cmd_buffer->cs, (index_va >> 32UL) & 0xFF);
+				radeon_emit(cmd_buffer->cs, indexCount);
+				radeon_emit(cmd_buffer->cs, V_0287F0_DI_SRC_SEL_DMA);
+
+			}
+		}
+	}
 
 	assert(cmd_buffer->cs->cdw <= cdw_max);
 	radv_cmd_buffer_trace_emit(cmd_buffer);
@@ -2776,20 +2828,44 @@ radv_emit_indirect_draw(struct radv_cmd_buffer *cmd_buffer,
 	radeon_emit(cs, indirect_va);
 	radeon_emit(cs, indirect_va >> 32);
 
-	radeon_emit(cs, PKT3(indexed ? PKT3_DRAW_INDEX_INDIRECT_MULTI :
-				       PKT3_DRAW_INDIRECT_MULTI,
-			     8, false));
-	radeon_emit(cs, 0);
-	radeon_emit(cs, (base_reg - SI_SH_REG_OFFSET) >> 2);
-	radeon_emit(cs, ((base_reg + 4) - SI_SH_REG_OFFSET) >> 2);
-	radeon_emit(cs, (((base_reg + 8) - SI_SH_REG_OFFSET) >> 2) |
-	                S_2C3_DRAW_INDEX_ENABLE(draw_id_enable) |
-	                S_2C3_COUNT_INDIRECT_ENABLE(!!count_va));
-	radeon_emit(cs, draw_count); /* count */
-	radeon_emit(cs, count_va); /* count_addr */
-	radeon_emit(cs, count_va >> 32);
-	radeon_emit(cs, stride); /* stride */
-	radeon_emit(cs, di_src_sel);
+	if (!cmd_buffer->state.subpass->view_mask) {
+
+		radeon_emit(cs, PKT3(indexed ? PKT3_DRAW_INDEX_INDIRECT_MULTI :
+		                               PKT3_DRAW_INDIRECT_MULTI,
+		                     8, false));
+		radeon_emit(cs, 0);
+		radeon_emit(cs, (base_reg - SI_SH_REG_OFFSET) >> 2);
+		radeon_emit(cs, ((base_reg + 4) - SI_SH_REG_OFFSET) >> 2);
+		radeon_emit(cs, (((base_reg + 8) - SI_SH_REG_OFFSET) >> 2) |
+		                S_2C3_DRAW_INDEX_ENABLE(draw_id_enable) |
+		                S_2C3_COUNT_INDIRECT_ENABLE(!!count_va));
+		radeon_emit(cs, draw_count); /* count */
+		radeon_emit(cs, count_va); /* count_addr */
+		radeon_emit(cs, count_va >> 32);
+		radeon_emit(cs, stride); /* stride */
+		radeon_emit(cs, di_src_sel);
+	} else {
+		for (unsigned i = 0; (1u << i) <= cmd_buffer->state.subpass->view_mask; ++i) {
+			if ((1u << i) & cmd_buffer->state.subpass->view_mask) {
+				radv_emit_view_index(cmd_buffer, i);
+
+				radeon_emit(cs, PKT3(indexed ? PKT3_DRAW_INDEX_INDIRECT_MULTI :
+				                               PKT3_DRAW_INDIRECT_MULTI,
+				                     8, false));
+				radeon_emit(cs, 0);
+				radeon_emit(cs, (base_reg - SI_SH_REG_OFFSET) >> 2);
+				radeon_emit(cs, ((base_reg + 4) - SI_SH_REG_OFFSET) >> 2);
+				radeon_emit(cs, (((base_reg + 8) - SI_SH_REG_OFFSET) >> 2) |
+				                S_2C3_DRAW_INDEX_ENABLE(draw_id_enable) |
+				                S_2C3_COUNT_INDIRECT_ENABLE(!!count_va));
+				radeon_emit(cs, draw_count); /* count */
+				radeon_emit(cs, count_va); /* count_addr */
+				radeon_emit(cs, count_va >> 32);
+				radeon_emit(cs, stride); /* stride */
+				radeon_emit(cs, di_src_sel);
+			}
+		}
+	}
 	radv_cmd_buffer_trace_emit(cmd_buffer);
 }
 
@@ -2806,7 +2882,7 @@ radv_cmd_draw_indirect_count(VkCommandBuffer                             command
 	radv_cmd_buffer_flush_state(cmd_buffer, false, false, true, 0);
 
 	MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws,
-							   cmd_buffer->cs, 14);
+							   cmd_buffer->cs, 14 * MAX_VIEWS);
 
 	radv_emit_indirect_draw(cmd_buffer, buffer, offset,
 	                        countBuffer, countBufferOffset, maxDrawCount, stride, false);
@@ -2830,7 +2906,7 @@ radv_cmd_draw_indexed_indirect_count(
 
 	index_va = cmd_buffer->state.index_va;
 
-	MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws, cmd_buffer->cs, 21);
+	MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws, cmd_buffer->cs, 21 * MAX_VIEWS);
 
 	radeon_emit(cmd_buffer->cs, PKT3(PKT3_INDEX_TYPE, 0, 0));
 	radeon_emit(cmd_buffer->cs, cmd_buffer->state.index_type);
diff --git a/src/amd/vulkan/radv_private.h b/src/amd/vulkan/radv_private.h
index fc8a467dc0f..e73ed008afe 100644
--- a/src/amd/vulkan/radv_private.h
+++ b/src/amd/vulkan/radv_private.h
@@ -86,6 +86,7 @@ typedef uint32_t xcb_window_t;
 #define MAX_SAMPLES_LOG2 4
 #define NUM_META_FS_KEYS 13
 #define RADV_MAX_DRM_DEVICES 8
+#define MAX_VIEWS        8
 
 #define NUM_DEPTH_CLEAR_PIPELINES 3
 
-- 
2.14.1



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