[Mesa-dev] [PATCH 4/4] radeonsi: get the raster config from AMDGPU on SI

[Nicolai Hähnle]

Patches 2-4:

Reviewed-by: Nicolai Hähnle <nicolai.haehnle at amd.com>


On 23.08.2017 22:44, Marek Olšák wrote:
> From: Marek Olšák <marek.olsak at amd.com>
> 
> Not sure yet if we wanna do this on CIK and VI too.
> ---
>   src/amd/common/ac_gpu_info.c            |  3 +++
>   src/amd/common/ac_gpu_info.h            |  2 ++
>   src/gallium/drivers/radeonsi/si_state.c | 17 +++++++++++++++++
>   3 files changed, 22 insertions(+)
> 
> diff --git a/src/amd/common/ac_gpu_info.c b/src/amd/common/ac_gpu_info.c
> index e55d864..84a54bb 100644
> --- a/src/amd/common/ac_gpu_info.c
> +++ b/src/amd/common/ac_gpu_info.c
> @@ -294,20 +294,23 @@ bool ac_query_gpu_info(int fd, amdgpu_device_handle dev,
>   	/* Get the number of good compute units. */
>   	info->num_good_compute_units = 0;
>   	for (i = 0; i < info->max_se; i++)
>   		for (j = 0; j < info->max_sh_per_se; j++)
>   			info->num_good_compute_units +=
>   				util_bitcount(amdinfo->cu_bitmap[i][j]);
>   
>   	memcpy(info->si_tile_mode_array, amdinfo->gb_tile_mode,
>   		sizeof(amdinfo->gb_tile_mode));
>   	info->enabled_rb_mask = amdinfo->enabled_rb_pipes_mask;
> +	memcpy(info->pa_sc_raster_config, amdinfo->pa_sc_raster_cfg,
> +	       sizeof(info->pa_sc_raster_config));
> +	info->pa_sc_raster_config_1 = amdinfo->pa_sc_raster_cfg1[0];
>   
>   	memcpy(info->cik_macrotile_mode_array, amdinfo->gb_macro_tile_mode,
>   		sizeof(amdinfo->gb_macro_tile_mode));
>   
>   	info->pte_fragment_size = alignment_info.size_local;
>   	info->gart_page_size = alignment_info.size_remote;
>   
>   	if (info->chip_class == SI)
>   		info->gfx_ib_pad_with_type2 = TRUE;
>   
> diff --git a/src/amd/common/ac_gpu_info.h b/src/amd/common/ac_gpu_info.h
> index 06b0c77..91d303a 100644
> --- a/src/amd/common/ac_gpu_info.h
> +++ b/src/amd/common/ac_gpu_info.h
> @@ -89,20 +89,22 @@ struct radeon_info {
>   	/* Render backends (color + depth blocks). */
>   	uint32_t                    r300_num_gb_pipes;
>   	uint32_t                    r300_num_z_pipes;
>   	uint32_t                    r600_gb_backend_map; /* R600 harvest config */
>   	bool                        r600_gb_backend_map_valid;
>   	uint32_t                    r600_num_banks;
>   	uint32_t                    num_render_backends;
>   	uint32_t                    num_tile_pipes; /* pipe count from PIPE_CONFIG */
>   	uint32_t                    pipe_interleave_bytes;
>   	uint32_t                    enabled_rb_mask; /* GCN harvest config */
> +	uint32_t                    pa_sc_raster_config[4]; /* per SE */
> +	uint32_t                    pa_sc_raster_config_1;
>   
>   	uint64_t                    max_alignment; /* from addrlib */
>   	/* Tile modes. */
>   	uint32_t                    si_tile_mode_array[32];
>   	uint32_t                    cik_macrotile_mode_array[16];
>   };
>   
>   bool ac_query_gpu_info(int fd, amdgpu_device_handle dev,
>   		       struct radeon_info *info,
>   		       struct amdgpu_gpu_info *amdinfo);
> diff --git a/src/gallium/drivers/radeonsi/si_state.c b/src/gallium/drivers/radeonsi/si_state.c
> index 4772df2..24e509c 100644
> --- a/src/gallium/drivers/radeonsi/si_state.c
> +++ b/src/gallium/drivers/radeonsi/si_state.c
> @@ -4414,20 +4414,37 @@ si_write_harvested_raster_configs(struct si_context *sctx,
>   			}
>   		}
>   
>   		si_pm4_set_reg(pm4, R_028354_PA_SC_RASTER_CONFIG_1, raster_config_1);
>   	}
>   }
>   
>   static void si_set_raster_config(struct si_context *sctx, struct si_pm4_state *pm4)
>   {
>   	struct si_screen *sscreen = sctx->screen;
> +
> +	/* On SI, set the raster config value from AMDGPU. */
> +	if (sscreen->b.info.drm_major == 3 && sscreen->b.chip_class == SI) {
> +		if (sscreen->b.info.max_se == 1) {
> +			si_pm4_set_reg(pm4, R_028350_PA_SC_RASTER_CONFIG,
> +				       sscreen->b.info.pa_sc_raster_config[0]);
> +		} else {
> +			for (unsigned se = 0; se < sscreen->b.info.max_se; se++) {
> +				si_set_grbm_gfx_index_se(sctx, pm4, se);
> +				si_pm4_set_reg(pm4, R_028350_PA_SC_RASTER_CONFIG,
> +					       sscreen->b.info.pa_sc_raster_config[se]);
> +			}
> +			si_set_grbm_gfx_index_se(sctx, pm4, ~0);
> +		}
> +		return;
> +	}
> +
>   	unsigned num_rb = MIN2(sctx->screen->b.info.num_render_backends, 16);
>   	unsigned rb_mask = sctx->screen->b.info.enabled_rb_mask;
>   	unsigned raster_config, raster_config_1;
>   
>   	switch (sctx->b.family) {
>   	case CHIP_TAHITI:
>   	case CHIP_PITCAIRN:
>   		raster_config = 0x2a00126a;
>   		raster_config_1 = 0x00000000;
>   		break;
> 


-- 
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