[Mesa-dev] [PATCH 20/47] i965/fs: Define new shader opcodes to set rounding modes

[Alejandro Piñeiro]

Although it is possible to emit them directly as AND/OR on brw_fs_nir,
having specific opcodes makes it easier to remove duplicate settings
later.

Signed-off-by:  Alejandro Piñeiro <apinheiro at igalia.com>
Signed-off-by:  Jose Maria Casanova Crespo <jmcasanova at igalia.com>
---
 src/intel/compiler/brw_eu.h             |  3 +++
 src/intel/compiler/brw_eu_defines.h     |  9 +++++++++
 src/intel/compiler/brw_eu_emit.c        | 19 +++++++++++++++++++
 src/intel/compiler/brw_fs_generator.cpp |  8 ++++++++
 src/intel/compiler/brw_shader.cpp       |  5 +++++
 5 files changed, 44 insertions(+)

diff --git a/src/intel/compiler/brw_eu.h b/src/intel/compiler/brw_eu.h
index a3a9c63239d..0a7f8020398 100644
--- a/src/intel/compiler/brw_eu.h
+++ b/src/intel/compiler/brw_eu.h
@@ -500,6 +500,9 @@ brw_broadcast(struct brw_codegen *p,
               struct brw_reg src,
               struct brw_reg idx);
 
+void
+brw_rounding_mode(struct brw_codegen *p,
+                  enum brw_rnd_mode mode);
 /***********************************************************************
  * brw_eu_util.c:
  */
diff --git a/src/intel/compiler/brw_eu_defines.h b/src/intel/compiler/brw_eu_defines.h
index 1af835d47ed..50435df2fcf 100644
--- a/src/intel/compiler/brw_eu_defines.h
+++ b/src/intel/compiler/brw_eu_defines.h
@@ -388,6 +388,9 @@ enum opcode {
    SHADER_OPCODE_TYPED_SURFACE_WRITE,
    SHADER_OPCODE_TYPED_SURFACE_WRITE_LOGICAL,
 
+   SHADER_OPCODE_RND_MODE_RTE,
+   SHADER_OPCODE_RND_MODE_RTZ,
+
    SHADER_OPCODE_MEMORY_FENCE,
 
    SHADER_OPCODE_GEN4_SCRATCH_READ,
@@ -1233,4 +1236,10 @@ enum brw_message_target {
 /* R0 */
 # define GEN7_GS_PAYLOAD_INSTANCE_ID_SHIFT		27
 
+enum PACKED brw_rnd_mode {
+   BRW_RND_MODE_UNSPECIFIED,
+   BRW_RND_MODE_RTE,
+   BRW_RND_MODE_RTZ,
+};
+
 #endif /* BRW_EU_DEFINES_H */
diff --git a/src/intel/compiler/brw_eu_emit.c b/src/intel/compiler/brw_eu_emit.c
index 0b0d67a5c56..07ad3d9384b 100644
--- a/src/intel/compiler/brw_eu_emit.c
+++ b/src/intel/compiler/brw_eu_emit.c
@@ -3723,3 +3723,22 @@ brw_WAIT(struct brw_codegen *p)
    brw_inst_set_exec_size(devinfo, insn, BRW_EXECUTE_1);
    brw_inst_set_mask_control(devinfo, insn, BRW_MASK_DISABLE);
 }
+
+void
+brw_rounding_mode(struct brw_codegen *p,
+                  enum brw_rnd_mode mode)
+{
+   switch (mode) {
+   case BRW_RND_MODE_UNSPECIFIED:
+      /* nothing to do here */
+      break;
+   case BRW_RND_MODE_RTZ:
+      brw_OR(p, brw_cr0_reg(0), brw_cr0_reg(0), brw_imm_ud(0x00000030u));
+      break;
+   case BRW_RND_MODE_RTE:
+      brw_AND(p, brw_cr0_reg(0), brw_cr0_reg(0), brw_imm_ud(0xffffffcfu));
+      break;
+   default:
+      unreachable("Not reached");
+   }
+}
diff --git a/src/intel/compiler/brw_fs_generator.cpp b/src/intel/compiler/brw_fs_generator.cpp
index 2ade486705b..e0bd191ea7e 100644
--- a/src/intel/compiler/brw_fs_generator.cpp
+++ b/src/intel/compiler/brw_fs_generator.cpp
@@ -2139,6 +2139,14 @@ fs_generator::generate_code(const cfg_t *cfg, int dispatch_width)
          brw_DIM(p, dst, retype(src[0], BRW_REGISTER_TYPE_F));
          break;
 
+      case SHADER_OPCODE_RND_MODE_RTE:
+         brw_rounding_mode(p, BRW_RND_MODE_RTE);
+         break;
+
+      case SHADER_OPCODE_RND_MODE_RTZ:
+         brw_rounding_mode(p, BRW_RND_MODE_RTZ);
+         break;
+
       default:
          unreachable("Unsupported opcode");
 
diff --git a/src/intel/compiler/brw_shader.cpp b/src/intel/compiler/brw_shader.cpp
index c62b8ba6140..f22e204e262 100644
--- a/src/intel/compiler/brw_shader.cpp
+++ b/src/intel/compiler/brw_shader.cpp
@@ -486,6 +486,11 @@ brw_instruction_name(const struct gen_device_info *devinfo, enum opcode op)
       return "tes_add_indirect_urb_offset";
    case TES_OPCODE_GET_PRIMITIVE_ID:
       return "tes_get_primitive_id";
+
+   case SHADER_OPCODE_RND_MODE_RTE:
+      return "round_mode_rte";
+   case SHADER_OPCODE_RND_MODE_RTZ:
+      return "round_mode_rtz";
    }
 
    unreachable("not reached");
-- 
2.11.0