[Mesa-dev] [PATCH 25/47] i965/fs: Adjust type_size/type_slots on store_ssbo
Alejandro PiƱeiro
apinheiro at igalia.com
Thu Aug 24 13:54:40 UTC 2017
---
src/intel/compiler/brw_fs_nir.cpp | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/src/intel/compiler/brw_fs_nir.cpp b/src/intel/compiler/brw_fs_nir.cpp
index 0e7738761c1..6791b2c7a4f 100644
--- a/src/intel/compiler/brw_fs_nir.cpp
+++ b/src/intel/compiler/brw_fs_nir.cpp
@@ -4089,11 +4089,10 @@ fs_visitor::nir_emit_intrinsic(const fs_builder &bld, nir_intrinsic_instr *instr
* Also, we have to suffle 64-bit data to be in the appropriate layout
* expected by our 32-bit write messages.
*/
- unsigned type_size = 4;
unsigned bit_size = instr->src[0].is_ssa ?
instr->src[0].ssa->bit_size : instr->src[0].reg.reg->bit_size;
+ unsigned type_size = bit_size / 8;
if (bit_size == 64) {
- type_size = 8;
fs_reg tmp =
fs_reg(VGRF, alloc.allocate(alloc.sizes[val_reg.nr]), val_reg.type);
shuffle_64bit_data_for_32bit_write(bld,
@@ -4103,7 +4102,8 @@ fs_visitor::nir_emit_intrinsic(const fs_builder &bld, nir_intrinsic_instr *instr
val_reg = tmp;
}
- unsigned type_slots = type_size / 4;
+ /* 16-bit types would use a minimum of 1 slot */
+ unsigned type_slots = MAX2(type_size / 4, 1);
/* Combine groups of consecutive enabled channels in one write
* message. We use ffs to find the first enabled channel and then ffs on
--
2.11.0
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