[Mesa-dev] [PATCH] radeonsi: set IF_THRESHOLD to 4

[Marek Olšák]

Acked-by: Marek Olšák <marek.olsak at amd.com>

Marek

On Thu, Aug 24, 2017 at 2:46 PM, Timothy Arceri <tarceri at itsqueeze.com> wrote:
> In 74e39de9324d it was set to 3 and it was reported that 4 caused
> tesseract to start spilling VGPRs. This no longer seems to be the
> case.
>
> Totals:
> SGPRS: 2787844 -> 2787764 (-0.00 %)
> VGPRS: 1713121 -> 1712717 (-0.02 %)
> Spilled SGPRs: 7532 -> 7532 (0.00 %)
> Spilled VGPRs: 49 -> 33 (-32.65 %)
> Private memory VGPRs: 2060 -> 2060 (0.00 %)
> Scratch size: 2200 -> 2180 (-0.91 %) dwords per thread
> Code Size: 79265520 -> 79248360 (-0.02 %) bytes
> LDS: 436 -> 436 (0.00 %) blocks
> Max Waves: 670535 -> 670608 (0.01 %)
> Wait states: 0 -> 0 (0.00 %)
>
> Before:
>  VGPR SPILLING APPS   Shaders SpillVGPR  PrivVGPR ScratchSize
>  EffectsCaveDemo          301         0       256       264
>  ReflectionsSubwayDemo    264         0       256       264
>  VehicleGame              295         0       128       132
>  bioshock-infinite       1140         0       448       516
>  dirt-showdown            453        33         0        28
>  gang-beasts              364         0       500       496
>  kerbal-space-program    1228         0       472       480
>  tomb-raider-ultra       1199        16         0        20
>
> After:
>  VGPR SPILLING APPS   Shaders SpillVGPR  PrivVGPR ScratchSize
>  EffectsCaveDemo          301         0       256       264
>  ReflectionsSubwayDemo    264         0       256       264
>  VehicleGame              295         0       128       132
>  bioshock-infinite       1140         0       448       516
>  dirt-showdown            453        33         0        28
>  gang-beasts              364         0       500       496
>  kerbal-space-program    1228         0       472       480
>
> The only change in VGPR spills is the elimination of all spills
> in Tomb Raider at Ultra settings. Closer examination shows that
> the shaders go over the limit because they contain three
> expressions a mul, rcp and ubo load. The ubo load is actually
> used elsewhere and is therefore stored in a temp already in IR
> such as tgsi but glsl ir counts it agaist the if cost.
>
> Cc: Marek Olšák <maraeo at gmail.com>
> ---
>  src/gallium/drivers/radeonsi/si_pipe.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/src/gallium/drivers/radeonsi/si_pipe.c b/src/gallium/drivers/radeonsi/si_pipe.c
> index 80a77a8f1f..1d2b7528ee 100644
> --- a/src/gallium/drivers/radeonsi/si_pipe.c
> +++ b/src/gallium/drivers/radeonsi/si_pipe.c
> @@ -769,21 +769,21 @@ static int si_get_shader_param(struct pipe_screen* pscreen,
>                 return SI_NUM_IMAGES;
>         case PIPE_SHADER_CAP_MAX_UNROLL_ITERATIONS_HINT:
>                 return 32;
>         case PIPE_SHADER_CAP_PREFERRED_IR:
>                 if (sscreen->b.debug_flags & DBG_NIR &&
>                     (shader == PIPE_SHADER_VERTEX ||
>                      shader == PIPE_SHADER_FRAGMENT))
>                         return PIPE_SHADER_IR_NIR;
>                 return PIPE_SHADER_IR_TGSI;
>         case PIPE_SHADER_CAP_LOWER_IF_THRESHOLD:
> -               return 3;
> +               return 4;
>
>         /* Supported boolean features. */
>         case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED:
>         case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED:
>         case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR:
>         case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR:
>         case PIPE_SHADER_CAP_INTEGERS:
>         case PIPE_SHADER_CAP_TGSI_FMA_SUPPORTED:
>         case PIPE_SHADER_CAP_TGSI_ANY_INOUT_DECL_RANGE:
>         case PIPE_SHADER_CAP_TGSI_SKIP_MERGE_REGISTERS:
> --
> 2.13.4
>