[Mesa-dev] [PATCH 6/7] i965/fs/nir: Don't stomp 64-bit values to D in get_nir_src

[Michael Schellenberger Costa]

Hi Jason,


given that 16bit types are already on the horizon a

switch(nir_src_bit_size(src))


seems more future-proof

--Michael


Am 28.08.2017 um 16:51 schrieb Jason Ekstrand:
> ---
>   src/intel/compiler/brw_fs_nir.cpp | 38 ++++++++++++++++++++++++++------------
>   1 file changed, 26 insertions(+), 12 deletions(-)
>
> diff --git a/src/intel/compiler/brw_fs_nir.cpp b/src/intel/compiler/brw_fs_nir.cpp
> index c46998a..a882979 100644
> --- a/src/intel/compiler/brw_fs_nir.cpp
> +++ b/src/intel/compiler/brw_fs_nir.cpp
> @@ -1438,11 +1438,24 @@ fs_visitor::get_nir_src(const nir_src &src)
>                      src.reg.base_offset * src.reg.reg->num_components);
>      }
>   
> -   /* to avoid floating-point denorm flushing problems, set the type by
> -    * default to D - instructions that need floating point semantics will set
> -    * this to F if they need to
> -    */
> -   return retype(reg, BRW_REGISTER_TYPE_D);
> +   if (nir_src_bit_size(src) == 32) {
> +      /* to avoid floating-point denorm flushing problems, set the type by
> +       * default to D - instructions that need floating point semantics will
> +       * set this to F if they need to
> +       */
> +      reg.type = BRW_REGISTER_TYPE_D;
> +   } else {
> +      /* We try to avoid dnorm issues for 64-bit too but we only have Q types
> +       * on gen8+ so gen7 gets DF.
> +       */
> +      assert(nir_src_bit_size(src) == 64);
> +      if (devinfo->gen >= 8)
> +         reg.type = BRW_REGISTER_TYPE_Q;
> +      else
> +         reg.type = BRW_REGISTER_TYPE_DF;
> +   }
> +
> +   return reg;
>   }
>   
>   /**
> @@ -1452,6 +1465,10 @@ fs_reg
>   fs_visitor::get_nir_src_imm(const nir_src &src)
>   {
>      nir_const_value *val = nir_src_as_const_value(src);
> +   /* This function shouldn't be called on anything which can even
> +    * possibly be 64 bits as it can't do what it claims.
> +    */
> +   assert(nir_src_bit_size(src) == 32);
>      return val ? fs_reg(brw_imm_d(val->i32[0])) : get_nir_src(src);
>   }
>   
> @@ -2643,8 +2660,7 @@ fs_visitor::nir_emit_tcs_intrinsic(const fs_builder &bld,
>                   */
>                  unsigned channel = iter * 2 + i;
>                  fs_reg dest = shuffle_64bit_data_for_32bit_write(bld,
> -                  retype(offset(value, bld, 2 * channel), BRW_REGISTER_TYPE_DF),
> -                  1);
> +                  offset(value, bld, channel), 1);
>   
>                  srcs[header_regs + (i + first_component) * 2] = dest;
>                  srcs[header_regs + (i + first_component) * 2 + 1] =
> @@ -3495,8 +3511,7 @@ fs_visitor::nir_emit_cs_intrinsic(const fs_builder &bld,
>         if (nir_src_bit_size(instr->src[0]) == 64) {
>            type_size = 8;
>            val_reg = shuffle_64bit_data_for_32bit_write(bld,
> -            retype(val_reg, BRW_REGISTER_TYPE_DF),
> -            instr->num_components);
> +            val_reg, instr->num_components);
>         }
>   
>         unsigned type_slots = type_size / 4;
> @@ -3995,8 +4010,7 @@ fs_visitor::nir_emit_intrinsic(const fs_builder &bld, nir_intrinsic_instr *instr
>         if (nir_src_bit_size(instr->src[0]) == 64) {
>            type_size = 8;
>            val_reg = shuffle_64bit_data_for_32bit_write(bld,
> -            retype(val_reg, BRW_REGISTER_TYPE_DF),
> -            instr->num_components);
> +            val_reg, instr->num_components);
>         }
>   
>         unsigned type_slots = type_size / 4;
> @@ -4053,7 +4067,7 @@ fs_visitor::nir_emit_intrinsic(const fs_builder &bld, nir_intrinsic_instr *instr
>         unsigned first_component = nir_intrinsic_component(instr);
>         if (nir_src_bit_size(instr->src[0]) == 64) {
>            fs_reg tmp = shuffle_64bit_data_for_32bit_write(bld,
> -            retype(src, BRW_REGISTER_TYPE_DF), num_components);
> +            src, num_components);
>            src = tmp;
>            num_components *= 2;
>         }