[Mesa-dev] [PATCH 6/8] radeonsi: make IBs and shader binaries read-only for the GPU

[Marek Olšák]

From: Marek Olšák <marek.olsak at amd.com>

Now Mesa can't corrupt them from the GPU.
---
 src/gallium/drivers/radeon/r600_buffer_common.c | 3 +++
 src/gallium/drivers/radeon/r600_pipe_common.h   | 1 +
 src/gallium/drivers/radeonsi/si_shader.c        | 8 +++++---
 src/gallium/winsys/amdgpu/drm/amdgpu_cs.c       | 1 +
 4 files changed, 10 insertions(+), 3 deletions(-)

diff --git a/src/gallium/drivers/radeon/r600_buffer_common.c b/src/gallium/drivers/radeon/r600_buffer_common.c
index ec282d5..55400ab 100644
--- a/src/gallium/drivers/radeon/r600_buffer_common.c
+++ b/src/gallium/drivers/radeon/r600_buffer_common.c
@@ -167,20 +167,23 @@ void si_init_resource_fields(struct si_screen *sscreen,
 
 	/* Displayable and shareable surfaces are not suballocated. */
 	if (res->b.b.bind & (PIPE_BIND_SHARED | PIPE_BIND_SCANOUT))
 		res->flags |= RADEON_FLAG_NO_SUBALLOC; /* shareable */
 	else
 		res->flags |= RADEON_FLAG_NO_INTERPROCESS_SHARING;
 
 	if (sscreen->debug_flags & DBG(NO_WC))
 		res->flags &= ~RADEON_FLAG_GTT_WC;
 
+	if (res->b.b.flags & R600_RESOURCE_FLAG_READ_ONLY)
+		res->flags |= RADEON_FLAG_READ_ONLY;
+
 	/* Set expected VRAM and GART usage for the buffer. */
 	res->vram_usage = 0;
 	res->gart_usage = 0;
 	res->max_forced_staging_uploads = 0;
 	res->b.max_forced_staging_uploads = 0;
 
 	if (res->domains & RADEON_DOMAIN_VRAM) {
 		res->vram_usage = size;
 
 		res->max_forced_staging_uploads =
diff --git a/src/gallium/drivers/radeon/r600_pipe_common.h b/src/gallium/drivers/radeon/r600_pipe_common.h
index 498a741..d1fdea0 100644
--- a/src/gallium/drivers/radeon/r600_pipe_common.h
+++ b/src/gallium/drivers/radeon/r600_pipe_common.h
@@ -46,20 +46,21 @@
 
 struct u_log_context;
 struct si_screen;
 struct si_context;
 
 #define R600_RESOURCE_FLAG_TRANSFER		(PIPE_RESOURCE_FLAG_DRV_PRIV << 0)
 #define R600_RESOURCE_FLAG_FLUSHED_DEPTH	(PIPE_RESOURCE_FLAG_DRV_PRIV << 1)
 #define R600_RESOURCE_FLAG_FORCE_TILING		(PIPE_RESOURCE_FLAG_DRV_PRIV << 2)
 #define R600_RESOURCE_FLAG_DISABLE_DCC		(PIPE_RESOURCE_FLAG_DRV_PRIV << 3)
 #define R600_RESOURCE_FLAG_UNMAPPABLE		(PIPE_RESOURCE_FLAG_DRV_PRIV << 4)
+#define R600_RESOURCE_FLAG_READ_ONLY		(PIPE_RESOURCE_FLAG_DRV_PRIV << 5)
 
 /* Debug flags. */
 enum {
 	/* Shader logging options: */
 	DBG_VS = PIPE_SHADER_VERTEX,
 	DBG_PS = PIPE_SHADER_FRAGMENT,
 	DBG_GS = PIPE_SHADER_GEOMETRY,
 	DBG_TCS = PIPE_SHADER_TESS_CTRL,
 	DBG_TES = PIPE_SHADER_TESS_EVAL,
 	DBG_CS = PIPE_SHADER_COMPUTE,
diff --git a/src/gallium/drivers/radeonsi/si_shader.c b/src/gallium/drivers/radeonsi/si_shader.c
index d3e5e97..a75feb2 100644
--- a/src/gallium/drivers/radeonsi/si_shader.c
+++ b/src/gallium/drivers/radeonsi/si_shader.c
@@ -5010,23 +5010,25 @@ int si_shader_binary_upload(struct si_screen *sscreen, struct si_shader *shader)
 
 	assert(!prolog || !prolog->rodata_size);
 	assert(!previous_stage || !previous_stage->rodata_size);
 	assert(!prolog2 || !prolog2->rodata_size);
 	assert((!prolog && !previous_stage && !prolog2 && !epilog) ||
 	       !mainb->rodata_size);
 	assert(!epilog || !epilog->rodata_size);
 
 	r600_resource_reference(&shader->bo, NULL);
 	shader->bo = (struct r600_resource*)
-		     pipe_buffer_create(&sscreen->b, 0,
-					PIPE_USAGE_IMMUTABLE,
-					align(bo_size, SI_CPDMA_ALIGNMENT));
+		     si_aligned_buffer_create(&sscreen->b,
+                                              R600_RESOURCE_FLAG_READ_ONLY,
+                                              PIPE_USAGE_IMMUTABLE,
+                                              align(bo_size, SI_CPDMA_ALIGNMENT),
+                                              256);
 	if (!shader->bo)
 		return -ENOMEM;
 
 	/* Upload. */
 	ptr = sscreen->ws->buffer_map(shader->bo->buf, NULL,
 					PIPE_TRANSFER_READ_WRITE |
 					PIPE_TRANSFER_UNSYNCHRONIZED);
 
 	/* Don't use util_memcpy_cpu_to_le32. LLVM binaries are
 	 * endian-independent. */
diff --git a/src/gallium/winsys/amdgpu/drm/amdgpu_cs.c b/src/gallium/winsys/amdgpu/drm/amdgpu_cs.c
index 089a358..63cd632 100644
--- a/src/gallium/winsys/amdgpu/drm/amdgpu_cs.c
+++ b/src/gallium/winsys/amdgpu/drm/amdgpu_cs.c
@@ -642,20 +642,21 @@ static bool amdgpu_ib_new_buffer(struct amdgpu_winsys *ws, struct amdgpu_ib *ib,
       buffer_size = MAX2(buffer_size, 8 * 1024 * 4);
       break;
    default:
       unreachable("unhandled IB type");
    }
 
    pb = ws->base.buffer_create(&ws->base, buffer_size,
                                ws->info.gart_page_size,
                                RADEON_DOMAIN_GTT,
                                RADEON_FLAG_NO_INTERPROCESS_SHARING |
+                               RADEON_FLAG_READ_ONLY |
                                (ring_type == RING_GFX ||
                                 ring_type == RING_COMPUTE ||
                                 ring_type == RING_DMA ?
                                    RADEON_FLAG_GTT_WC : 0));
    if (!pb)
       return false;
 
    mapped = ws->base.buffer_map(pb, NULL, PIPE_TRANSFER_WRITE);
    if (!mapped) {
       pb_reference(&pb, NULL);
-- 
2.7.4