[Mesa-dev] [PATCH 1/2] radv: enable lowering of nir_op_bitfield_insert

[Samuel Pitoiset]

Otherwise it's replaced by
"vec1 32 ssa_108 = load_const (0x00000000 /* 0.000000 */)", which
looks clearly wrong.

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=104119
Signed-off-by: Samuel Pitoiset <samuel.pitoiset at gmail.com>
---
 src/amd/vulkan/radv_shader.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/src/amd/vulkan/radv_shader.c b/src/amd/vulkan/radv_shader.c
index 4a3fdfa80e..0b19d23fa2 100644
--- a/src/amd/vulkan/radv_shader.c
+++ b/src/amd/vulkan/radv_shader.c
@@ -66,6 +66,7 @@ static const struct nir_shader_compiler_options nir_options = {
 	.lower_extract_byte = true,
 	.lower_extract_word = true,
 	.lower_ffma = true,
+	.lower_bitfield_insert = true,
 	.max_unroll_iterations = 32
 };
 
-- 
2.15.1