[Mesa-dev] [PATCH 1/2] radv: enable lowering of nir_op_bitfield_insert

Samuel Pitoiset samuel.pitoiset at gmail.com
Wed Dec 6 12:47:44 UTC 2017

On 12/06/2017 01:04 PM, James Legg wrote:
> On Tue, 2017-12-05 at 14:24 -0500, Connor Abbott wrote:
>> lower_bitfield_insert lowers nir_op_bitfield_insert to DX10-style
>> nir_op_bfi and nir_op_bfm, both of which aren't handled by
>> ac_nir_to_llvm, so unless I'm missing something this will just break
>> them even harder. We probably should use this lowering after adding
>> support for bfi and bfm, since AMD does have native instructions for
>> bfi and bfm, but first I'd like to see the actual bug fixed. Have you
>> tried running it with NIR_PRINT=true to pin down which optimization
>> pass is going wrong?
> I've identified the constant folding pass as the culprit and fixed the
> incorrect logic for bitfield_insert with this patch:
>      nir/opcodes: Fix constant-folding of bitfield_insert
>      https://patchwork.freedesktop.org/patch/191977/

Your fix looks much better, thanks!

> James

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