[Mesa-dev] [PATCH 10/18] ac: add {tcs,tes}_patch_id to the abi

Timothy Arceri tarceri at itsqueeze.com
Mon Dec 11 02:43:20 UTC 2017


---
 src/amd/common/ac_nir_to_llvm.c                   | 22 +++++++++++-----------
 src/amd/common/ac_shader_abi.h                    |  2 ++
 src/gallium/drivers/radeonsi/si_shader.c          | 17 ++++++++---------
 src/gallium/drivers/radeonsi/si_shader_internal.h |  2 --
 4 files changed, 21 insertions(+), 22 deletions(-)

diff --git a/src/amd/common/ac_nir_to_llvm.c b/src/amd/common/ac_nir_to_llvm.c
index 28edf819c58..9641b43421d 100644
--- a/src/amd/common/ac_nir_to_llvm.c
+++ b/src/amd/common/ac_nir_to_llvm.c
@@ -103,24 +103,22 @@ struct nir_to_llvm_context {
 	LLVMValueRef ls_out_layout;
 	LLVMValueRef es2gs_offset;
 
 	LLVMValueRef tcs_offchip_layout;
 	LLVMValueRef tcs_out_offsets;
 	LLVMValueRef tcs_out_layout;
 	LLVMValueRef tcs_in_layout;
 	LLVMValueRef oc_lds;
 	LLVMValueRef merged_wave_info;
 	LLVMValueRef tess_factor_offset;
-	LLVMValueRef tcs_patch_id;
 	LLVMValueRef tcs_rel_ids;
 	LLVMValueRef tes_rel_patch_id;
-	LLVMValueRef tes_patch_id;
 	LLVMValueRef tes_u;
 	LLVMValueRef tes_v;
 
 	LLVMValueRef gsvs_ring_stride;
 	LLVMValueRef gsvs_num_entries;
 	LLVMValueRef gs2vs_offset;
 	LLVMValueRef gs_wave_id;
 	LLVMValueRef gs_vtx_offset[6];
 
 	LLVMValueRef esgs_ring;
@@ -782,57 +780,57 @@ static void create_function(struct nir_to_llvm_context *ctx,
 			radv_define_vs_user_sgprs_phase1(ctx, stage, has_previous_stage, previous_stage, &args);
 			add_user_sgpr_argument(&args, ctx->ac.i32, &ctx->ls_out_layout); // ls out layout
 
 			add_user_sgpr_argument(&args, ctx->ac.i32, &ctx->tcs_offchip_layout); // tcs offchip layout
 			add_user_sgpr_argument(&args, ctx->ac.i32, &ctx->tcs_out_offsets); // tcs out offsets
 			add_user_sgpr_argument(&args, ctx->ac.i32, &ctx->tcs_out_layout); // tcs out layout
 			add_user_sgpr_argument(&args, ctx->ac.i32, &ctx->tcs_in_layout); // tcs in layout
 			if (ctx->shader_info->info.needs_multiview_view_index)
 				add_user_sgpr_argument(&args, ctx->ac.i32, &ctx->view_index);
 
-			add_vgpr_argument(&args, ctx->ac.i32, &ctx->tcs_patch_id); // patch id
+			add_vgpr_argument(&args, ctx->ac.i32, &ctx->abi.tcs_patch_id); // patch id
 			add_vgpr_argument(&args, ctx->ac.i32, &ctx->tcs_rel_ids); // rel ids;
 			add_vgpr_argument(&args, ctx->ac.i32, &ctx->abi.vertex_id); // vertex id
 			add_vgpr_argument(&args, ctx->ac.i32, &ctx->rel_auto_id); // rel auto id
 			add_vgpr_argument(&args, ctx->ac.i32, &ctx->vs_prim_id); // vs prim id
 			add_vgpr_argument(&args, ctx->ac.i32, &ctx->abi.instance_id); // instance id
 		} else {
 			radv_define_common_user_sgprs_phase1(ctx, stage, has_previous_stage, previous_stage, &user_sgpr_info, &args, &desc_sets);
 			add_user_sgpr_argument(&args, ctx->ac.i32, &ctx->tcs_offchip_layout); // tcs offchip layout
 			add_user_sgpr_argument(&args, ctx->ac.i32, &ctx->tcs_out_offsets); // tcs out offsets
 			add_user_sgpr_argument(&args, ctx->ac.i32, &ctx->tcs_out_layout); // tcs out layout
 			add_user_sgpr_argument(&args, ctx->ac.i32, &ctx->tcs_in_layout); // tcs in layout
 			if (ctx->shader_info->info.needs_multiview_view_index)
 				add_user_sgpr_argument(&args, ctx->ac.i32, &ctx->view_index);
 			add_sgpr_argument(&args, ctx->ac.i32, &ctx->oc_lds); // param oc lds
 			add_sgpr_argument(&args, ctx->ac.i32, &ctx->tess_factor_offset); // tess factor offset
-			add_vgpr_argument(&args, ctx->ac.i32, &ctx->tcs_patch_id); // patch id
+			add_vgpr_argument(&args, ctx->ac.i32, &ctx->abi.tcs_patch_id); // patch id
 			add_vgpr_argument(&args, ctx->ac.i32, &ctx->tcs_rel_ids); // rel ids;
 		}
 		break;
 	case MESA_SHADER_TESS_EVAL:
 		radv_define_common_user_sgprs_phase1(ctx, stage, has_previous_stage, previous_stage, &user_sgpr_info, &args, &desc_sets);
 		add_user_sgpr_argument(&args, ctx->ac.i32, &ctx->tcs_offchip_layout); // tcs offchip layout
 		if (ctx->shader_info->info.needs_multiview_view_index || (!ctx->options->key.tes.as_es && ctx->options->key.has_multiview_view_index))
 			add_user_sgpr_argument(&args, ctx->ac.i32, &ctx->view_index);
 		if (ctx->options->key.tes.as_es) {
 			add_sgpr_argument(&args, ctx->ac.i32, &ctx->oc_lds); // OC LDS
 			add_sgpr_argument(&args, ctx->ac.i32, NULL); //
 			add_sgpr_argument(&args, ctx->ac.i32, &ctx->es2gs_offset); // es2gs offset
 		} else {
 			add_sgpr_argument(&args, ctx->ac.i32, NULL); //
 			add_sgpr_argument(&args, ctx->ac.i32, &ctx->oc_lds); // OC LDS
 		}
 		add_vgpr_argument(&args, ctx->ac.f32, &ctx->tes_u); // tes_u
 		add_vgpr_argument(&args, ctx->ac.f32, &ctx->tes_v); // tes_v
 		add_vgpr_argument(&args, ctx->ac.i32, &ctx->tes_rel_patch_id); // tes rel patch id
-		add_vgpr_argument(&args, ctx->ac.i32, &ctx->tes_patch_id); // tes patch id
+		add_vgpr_argument(&args, ctx->ac.i32, &ctx->abi.tes_patch_id); // tes patch id
 		break;
 	case MESA_SHADER_GEOMETRY:
 		if (has_previous_stage) {
 			// First 6 system regs
 			add_sgpr_argument(&args, ctx->ac.i32, &ctx->gs2vs_offset); // tess factor offset
 			add_sgpr_argument(&args, ctx->ac.i32, &ctx->merged_wave_info); // merged wave info
 			add_sgpr_argument(&args, ctx->ac.i32, &ctx->oc_lds); // param oc lds
 
 			add_sgpr_argument(&args, ctx->ac.i32, NULL); // scratch offset
 			add_sgpr_argument(&args, ctx->ac.i32, NULL); // unknown
@@ -856,21 +854,21 @@ static void create_function(struct nir_to_llvm_context *ctx,
 
 			if (previous_stage == MESA_SHADER_VERTEX) {
 				add_vgpr_argument(&args, ctx->ac.i32, &ctx->abi.vertex_id); // vertex id
 				add_vgpr_argument(&args, ctx->ac.i32, &ctx->rel_auto_id); // rel auto id
 				add_vgpr_argument(&args, ctx->ac.i32, &ctx->vs_prim_id); // vs prim id
 				add_vgpr_argument(&args, ctx->ac.i32, &ctx->abi.instance_id); // instance id
 			} else {
 				add_vgpr_argument(&args, ctx->ac.f32, &ctx->tes_u); // tes_u
 				add_vgpr_argument(&args, ctx->ac.f32, &ctx->tes_v); // tes_v
 				add_vgpr_argument(&args, ctx->ac.i32, &ctx->tes_rel_patch_id); // tes rel patch id
-				add_vgpr_argument(&args, ctx->ac.i32, &ctx->tes_patch_id); // tes patch id
+				add_vgpr_argument(&args, ctx->ac.i32, &ctx->abi.tes_patch_id); // tes patch id
 			}
 		} else {
 			radv_define_common_user_sgprs_phase1(ctx, stage, has_previous_stage, previous_stage, &user_sgpr_info, &args, &desc_sets);
 			radv_define_vs_user_sgprs_phase1(ctx, stage, has_previous_stage, previous_stage, &args);
 			add_user_sgpr_argument(&args, ctx->ac.i32, &ctx->gsvs_ring_stride); // gsvs stride
 			add_user_sgpr_argument(&args, ctx->ac.i32, &ctx->gsvs_num_entries); // gsvs num entires
 			if (ctx->shader_info->info.needs_multiview_view_index)
 				add_user_sgpr_argument(&args, ctx->ac.i32, &ctx->view_index);
 			add_sgpr_argument(&args, ctx->ac.i32, &ctx->gs2vs_offset); // gs2vs offset
 			add_sgpr_argument(&args, ctx->ac.i32, &ctx->gs_wave_id); // wave id
@@ -4082,25 +4080,27 @@ static void visit_intrinsic(struct ac_nir_context *ctx,
 			result = unpack_param(&ctx->ac, ctx->nctx->tcs_rel_ids, 8, 5);
 		else
 			result = ctx->abi->gs_invocation_id;
 		break;
 	case nir_intrinsic_load_primitive_id:
 		if (ctx->stage == MESA_SHADER_GEOMETRY) {
 			if (ctx->nctx)
 				ctx->nctx->shader_info->gs.uses_prim_id = true;
 			result = ctx->abi->gs_prim_id;
 		} else if (ctx->stage == MESA_SHADER_TESS_CTRL) {
-			ctx->nctx->shader_info->tcs.uses_prim_id = true;
-			result = ctx->nctx->tcs_patch_id;
+			if (ctx->nctx)
+				ctx->nctx->shader_info->tcs.uses_prim_id = true;
+			result = ctx->abi->tcs_patch_id;
 		} else if (ctx->stage == MESA_SHADER_TESS_EVAL) {
-			ctx->nctx->shader_info->tcs.uses_prim_id = true;
-			result = ctx->nctx->tes_patch_id;
+			if (ctx->nctx)
+				ctx->nctx->shader_info->tcs.uses_prim_id = true;
+			result = ctx->abi->tes_patch_id;
 		} else
 			fprintf(stderr, "Unknown primitive id intrinsic: %d", ctx->stage);
 		break;
 	case nir_intrinsic_load_sample_id:
 		result = unpack_param(&ctx->ac, ctx->abi->ancillary, 8, 4);
 		break;
 	case nir_intrinsic_load_sample_pos:
 		result = load_sample_pos(ctx);
 		break;
 	case nir_intrinsic_load_sample_mask_in:
@@ -6430,21 +6430,21 @@ ac_nir_get_max_workgroup_size(enum chip_class chip_class,
 static void ac_nir_fixup_ls_hs_input_vgprs(struct nir_to_llvm_context *ctx)
 {
 	LLVMValueRef count = ac_build_bfe(&ctx->ac, ctx->merged_wave_info,
 	                                  LLVMConstInt(ctx->ac.i32, 8, false),
 	                                  LLVMConstInt(ctx->ac.i32, 8, false), false);
 	LLVMValueRef hs_empty = LLVMBuildICmp(ctx->ac.builder, LLVMIntEQ, count,
 	                                      LLVMConstInt(ctx->ac.i32, 0, false), "");
 	ctx->abi.instance_id = LLVMBuildSelect(ctx->ac.builder, hs_empty, ctx->rel_auto_id, ctx->abi.instance_id, "");
 	ctx->vs_prim_id = LLVMBuildSelect(ctx->ac.builder, hs_empty, ctx->abi.vertex_id, ctx->vs_prim_id, "");
 	ctx->rel_auto_id = LLVMBuildSelect(ctx->ac.builder, hs_empty, ctx->tcs_rel_ids, ctx->rel_auto_id, "");
-	ctx->abi.vertex_id = LLVMBuildSelect(ctx->ac.builder, hs_empty, ctx->tcs_patch_id, ctx->abi.vertex_id, "");
+	ctx->abi.vertex_id = LLVMBuildSelect(ctx->ac.builder, hs_empty, ctx->abi.tcs_patch_id, ctx->abi.vertex_id, "");
 }
 
 static void prepare_gs_input_vgprs(struct nir_to_llvm_context *ctx)
 {
 	for(int i = 5; i >= 0; --i) {
 		ctx->gs_vtx_offset[i] = ac_build_bfe(&ctx->ac, ctx->gs_vtx_offset[i & ~1],
 		                                     LLVMConstInt(ctx->ac.i32, (i & 1) * 16, false),
 		                                     LLVMConstInt(ctx->ac.i32, 16, false), false);
 	}
 
diff --git a/src/amd/common/ac_shader_abi.h b/src/amd/common/ac_shader_abi.h
index c4d9926e82b..2aadc20d403 100644
--- a/src/amd/common/ac_shader_abi.h
+++ b/src/amd/common/ac_shader_abi.h
@@ -35,20 +35,22 @@ enum ac_descriptor_type {
 
 /* Document the shader ABI during compilation. This is what allows radeonsi and
  * radv to share a compiler backend.
  */
 struct ac_shader_abi {
 	LLVMValueRef base_vertex;
 	LLVMValueRef start_instance;
 	LLVMValueRef draw_id;
 	LLVMValueRef vertex_id;
 	LLVMValueRef instance_id;
+	LLVMValueRef tcs_patch_id;
+	LLVMValueRef tes_patch_id;
 	LLVMValueRef gs_prim_id;
 	LLVMValueRef gs_invocation_id;
 	LLVMValueRef frag_pos[4];
 	LLVMValueRef front_face;
 	LLVMValueRef ancillary;
 	LLVMValueRef sample_coverage;
 
 	/* For VS and PS: pre-loaded shader inputs.
 	 *
 	 * Currently only used for NIR shaders; indexed by variables'
diff --git a/src/gallium/drivers/radeonsi/si_shader.c b/src/gallium/drivers/radeonsi/si_shader.c
index 308c8b99151..ce01b781799 100644
--- a/src/gallium/drivers/radeonsi/si_shader.c
+++ b/src/gallium/drivers/radeonsi/si_shader.c
@@ -755,25 +755,23 @@ static LLVMValueRef get_primitive_id(struct si_shader_context *ctx,
 				     unsigned swizzle)
 {
 	if (swizzle > 0)
 		return ctx->i32_0;
 
 	switch (ctx->type) {
 	case PIPE_SHADER_VERTEX:
 		return LLVMGetParam(ctx->main_fn,
 				    ctx->param_vs_prim_id);
 	case PIPE_SHADER_TESS_CTRL:
-		return LLVMGetParam(ctx->main_fn,
-				    ctx->param_tcs_patch_id);
+		return ctx->abi.tcs_patch_id;
 	case PIPE_SHADER_TESS_EVAL:
-		return LLVMGetParam(ctx->main_fn,
-				    ctx->param_tes_patch_id);
+		return ctx->abi.tes_patch_id;
 	case PIPE_SHADER_GEOMETRY:
 		return ctx->abi.gs_prim_id;
 	default:
 		assert(0);
 		return ctx->i32_0;
 	}
 }
 
 /**
  * Return the value of tgsi_ind_register for indexing.
@@ -3365,22 +3363,23 @@ static void si_set_ls_return_value_for_tcs(struct si_shader_context *ctx)
 	ret = si_insert_input_ret(ctx, ret, ctx->param_tcs_factor_addr_base64k,
 				  8 + GFX9_SGPR_TCS_FACTOR_ADDR_BASE64K);
 
 	unsigned desc_param = ctx->param_tcs_factor_addr_base64k + 2;
 	ret = si_insert_input_ptr_as_2xi32(ctx, ret, desc_param,
 					   8 + GFX9_SGPR_TCS_CONST_AND_SHADER_BUFFERS);
 	ret = si_insert_input_ptr_as_2xi32(ctx, ret, desc_param + 1,
 					   8 + GFX9_SGPR_TCS_SAMPLERS_AND_IMAGES);
 
 	unsigned vgpr = 8 + GFX9_TCS_NUM_USER_SGPR;
-	ret = si_insert_input_ret_float(ctx, ret,
-					ctx->param_tcs_patch_id, vgpr++);
+	ret = LLVMBuildInsertValue(ctx->ac.builder, ret,
+				   ac_to_float(&ctx->ac, ctx->abi.tcs_patch_id),
+				   vgpr++, "");
 	ret = si_insert_input_ret_float(ctx, ret,
 					ctx->param_tcs_rel_ids, vgpr++);
 	ctx->return_value = ret;
 }
 
 /* Pass GS inputs from ES to GS on GFX9. */
 static void si_set_es_return_value_for_gs(struct si_shader_context *ctx)
 {
 	LLVMValueRef ret = ctx->return_value;
 
@@ -4653,21 +4652,21 @@ static void declare_vs_input_vgprs(struct si_shader_context *ctx,
 		*num_prolog_vgprs += shader->selector->info.num_inputs;
 	}
 }
 
 static void declare_tes_input_vgprs(struct si_shader_context *ctx,
 				    struct si_function_info *fninfo)
 {
 	ctx->param_tes_u = add_arg(fninfo, ARG_VGPR, ctx->f32);
 	ctx->param_tes_v = add_arg(fninfo, ARG_VGPR, ctx->f32);
 	ctx->param_tes_rel_patch_id = add_arg(fninfo, ARG_VGPR, ctx->i32);
-	ctx->param_tes_patch_id = add_arg(fninfo, ARG_VGPR, ctx->i32);
+	add_arg_assign(fninfo, ARG_VGPR, ctx->i32, &ctx->abi.tes_patch_id);
 }
 
 enum {
 	/* Convenient merged shader definitions. */
 	SI_SHADER_MERGED_VERTEX_TESSCTRL = PIPE_SHADER_TYPES,
 	SI_SHADER_MERGED_VERTEX_OR_TESSEVAL_GEOMETRY,
 };
 
 static void create_function(struct si_shader_context *ctx)
 {
@@ -4750,21 +4749,21 @@ static void create_function(struct si_shader_context *ctx)
 		ctx->param_tcs_offchip_layout = add_arg(&fninfo, ARG_SGPR, ctx->i32);
 		ctx->param_tcs_out_lds_offsets = add_arg(&fninfo, ARG_SGPR, ctx->i32);
 		ctx->param_tcs_out_lds_layout = add_arg(&fninfo, ARG_SGPR, ctx->i32);
 		ctx->param_vs_state_bits = add_arg(&fninfo, ARG_SGPR, ctx->i32);
 		ctx->param_tcs_offchip_addr_base64k = add_arg(&fninfo, ARG_SGPR, ctx->i32);
 		ctx->param_tcs_factor_addr_base64k = add_arg(&fninfo, ARG_SGPR, ctx->i32);
 		ctx->param_tcs_offchip_offset = add_arg(&fninfo, ARG_SGPR, ctx->i32);
 		ctx->param_tcs_factor_offset = add_arg(&fninfo, ARG_SGPR, ctx->i32);
 
 		/* VGPRs */
-		ctx->param_tcs_patch_id = add_arg(&fninfo, ARG_VGPR, ctx->i32);
+		add_arg_assign(&fninfo, ARG_VGPR, ctx->i32, &ctx->abi.tcs_patch_id);
 		ctx->param_tcs_rel_ids = add_arg(&fninfo, ARG_VGPR, ctx->i32);
 
 		/* param_tcs_offchip_offset and param_tcs_factor_offset are
 		 * placed after the user SGPRs.
 		 */
 		for (i = 0; i < GFX6_TCS_NUM_USER_SGPR + 2; i++)
 			returns[num_returns++] = ctx->i32; /* SGPRs */
 		for (i = 0; i < 11; i++)
 			returns[num_returns++] = ctx->f32; /* VGPRs */
 		break;
@@ -4789,21 +4788,21 @@ static void create_function(struct si_shader_context *ctx)
 		ctx->param_tcs_out_lds_offsets = add_arg(&fninfo, ARG_SGPR, ctx->i32);
 		ctx->param_tcs_out_lds_layout = add_arg(&fninfo, ARG_SGPR, ctx->i32);
 		ctx->param_tcs_offchip_addr_base64k = add_arg(&fninfo, ARG_SGPR, ctx->i32);
 		ctx->param_tcs_factor_addr_base64k = add_arg(&fninfo, ARG_SGPR, ctx->i32);
 		add_arg(&fninfo, ARG_SGPR, ctx->i32); /* unused */
 
 		declare_per_stage_desc_pointers(ctx, &fninfo,
 						ctx->type == PIPE_SHADER_TESS_CTRL);
 
 		/* VGPRs (first TCS, then VS) */
-		ctx->param_tcs_patch_id = add_arg(&fninfo, ARG_VGPR, ctx->i32);
+		add_arg_assign(&fninfo, ARG_VGPR, ctx->i32, &ctx->abi.tcs_patch_id);
 		ctx->param_tcs_rel_ids = add_arg(&fninfo, ARG_VGPR, ctx->i32);
 
 		if (ctx->type == PIPE_SHADER_VERTEX) {
 			declare_vs_input_vgprs(ctx, &fninfo,
 					       &num_prolog_vgprs);
 
 			/* LS return values are inputs to the TCS main shader part. */
 			for (i = 0; i < 8 + GFX9_TCS_NUM_USER_SGPR; i++)
 				returns[num_returns++] = ctx->i32; /* SGPRs */
 			for (i = 0; i < 2; i++)
diff --git a/src/gallium/drivers/radeonsi/si_shader_internal.h b/src/gallium/drivers/radeonsi/si_shader_internal.h
index d600982c9bb..5c0d22dcd7f 100644
--- a/src/gallium/drivers/radeonsi/si_shader_internal.h
+++ b/src/gallium/drivers/radeonsi/si_shader_internal.h
@@ -162,28 +162,26 @@ struct si_shader_context {
 	/* Layout of TCS outputs / TES inputs:
 	 *   [0:12] = stride between output patches in DW, num_outputs * num_vertices * 4
 	 *            max = 32*32*4 + 32*4
 	 *   [26:31] = gl_PatchVerticesIn, max = 32
 	 */
 	int param_tcs_out_lds_layout;
 	int param_tcs_offchip_addr_base64k;
 	int param_tcs_factor_addr_base64k;
 	int param_tcs_offchip_offset;
 	int param_tcs_factor_offset;
-	int param_tcs_patch_id;
 	int param_tcs_rel_ids;
 
 	/* API TES */
 	int param_tes_u;
 	int param_tes_v;
 	int param_tes_rel_patch_id;
-	int param_tes_patch_id;
 	/* HW ES */
 	int param_es2gs_offset;
 	/* API GS */
 	int param_gs2vs_offset;
 	int param_gs_wave_id; /* GFX6 */
 	LLVMValueRef gs_vtx_offset[6]; /* in dwords (GFX6) */
 	int param_gs_vtx01_offset; /* in dwords (GFX9) */
 	int param_gs_vtx23_offset; /* in dwords (GFX9) */
 	int param_gs_vtx45_offset; /* in dwords (GFX9) */
 	/* CS */
-- 
2.14.3



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