[Mesa-dev] [PATCH 1/3] gallium/util: add util_num_layers helper
Marek Olšák
maraeo at gmail.com
Tue Dec 12 21:47:03 UTC 2017
From: Marek Olšák <marek.olsak at amd.com>
---
src/gallium/auxiliary/util/u_blitter.c | 4 ++--
src/gallium/auxiliary/util/u_gen_mipmap.c | 4 ++--
src/gallium/auxiliary/util/u_inlines.h | 8 +++++++-
src/gallium/drivers/r600/r600_texture.c | 8 ++++----
src/gallium/drivers/radeon/r600_texture.c | 8 ++++----
src/gallium/drivers/radeonsi/si_clear.c | 2 +-
src/gallium/drivers/rbug/rbug_core.c | 2 +-
7 files changed, 21 insertions(+), 15 deletions(-)
diff --git a/src/gallium/auxiliary/util/u_blitter.c b/src/gallium/auxiliary/util/u_blitter.c
index 476ef08..c7cc11d 100644
--- a/src/gallium/auxiliary/util/u_blitter.c
+++ b/src/gallium/auxiliary/util/u_blitter.c
@@ -2070,22 +2070,22 @@ void util_blitter_generate_mipmap(struct blitter_context *blitter,
struct pipe_box dstbox = {0}, srcbox = {0};
unsigned dst_level = src_level + 1;
dstbox.width = u_minify(tex->width0, dst_level);
dstbox.height = u_minify(tex->height0, dst_level);
srcbox.width = u_minify(tex->width0, src_level);
srcbox.height = u_minify(tex->height0, src_level);
if (target == PIPE_TEXTURE_3D) {
- dstbox.depth = util_max_layer(tex, dst_level) + 1;
- srcbox.depth = util_max_layer(tex, src_level) + 1;
+ dstbox.depth = util_num_layers(tex, dst_level);
+ srcbox.depth = util_num_layers(tex, src_level);
} else {
dstbox.z = srcbox.z = first_layer;
dstbox.depth = srcbox.depth = last_layer - first_layer + 1;
}
/* Initialize the surface. */
util_blitter_default_dst_texture(&dst_templ, tex, dst_level,
first_layer);
dst_templ.format = format;
dst_view = pipe->create_surface(pipe, tex, &dst_templ);
diff --git a/src/gallium/auxiliary/util/u_gen_mipmap.c b/src/gallium/auxiliary/util/u_gen_mipmap.c
index aa8eaeb..3c55d9f 100644
--- a/src/gallium/auxiliary/util/u_gen_mipmap.c
+++ b/src/gallium/auxiliary/util/u_gen_mipmap.c
@@ -106,22 +106,22 @@ util_gen_mipmap(struct pipe_context *pipe, struct pipe_resource *pt,
blit.src.box.width = u_minify(pt->width0, blit.src.level);
blit.src.box.height = u_minify(pt->height0, blit.src.level);
blit.dst.box.width = u_minify(pt->width0, blit.dst.level);
blit.dst.box.height = u_minify(pt->height0, blit.dst.level);
if (pt->target == PIPE_TEXTURE_3D) {
/* generate all layers/slices at once */
blit.src.box.z = blit.dst.box.z = 0;
- blit.src.box.depth = util_max_layer(pt, blit.src.level)+1;
- blit.dst.box.depth = util_max_layer(pt, blit.dst.level)+1;
+ blit.src.box.depth = util_num_layers(pt, blit.src.level);
+ blit.dst.box.depth = util_num_layers(pt, blit.dst.level);
}
else {
blit.src.box.z = blit.dst.box.z = first_layer;
blit.src.box.depth = blit.dst.box.depth =
(last_layer + 1 - first_layer);
}
pipe->blit(pipe, &blit);
}
return TRUE;
diff --git a/src/gallium/auxiliary/util/u_inlines.h b/src/gallium/auxiliary/util/u_inlines.h
index 790352d..4ba6ad7 100644
--- a/src/gallium/auxiliary/util/u_inlines.h
+++ b/src/gallium/auxiliary/util/u_inlines.h
@@ -659,27 +659,33 @@ util_max_layer(const struct pipe_resource *r, unsigned level)
/* fall-through */
case PIPE_TEXTURE_1D_ARRAY:
case PIPE_TEXTURE_2D_ARRAY:
case PIPE_TEXTURE_CUBE_ARRAY:
return r->array_size - 1;
default:
return 0;
}
}
+static inline unsigned
+util_num_layers(const struct pipe_resource *r, unsigned level)
+{
+ return util_max_layer(r, level) + 1;
+}
+
static inline bool
util_texrange_covers_whole_level(const struct pipe_resource *tex,
unsigned level, unsigned x, unsigned y,
unsigned z, unsigned width,
unsigned height, unsigned depth)
{
return x == 0 && y == 0 && z == 0 &&
width == u_minify(tex->width0, level) &&
height == u_minify(tex->height0, level) &&
- depth == util_max_layer(tex, level) + 1;
+ depth == util_num_layers(tex, level);
}
#ifdef __cplusplus
}
#endif
#endif /* U_INLINES_H */
diff --git a/src/gallium/drivers/r600/r600_texture.c b/src/gallium/drivers/r600/r600_texture.c
index 3895d53..03cdcd2 100644
--- a/src/gallium/drivers/r600/r600_texture.c
+++ b/src/gallium/drivers/r600/r600_texture.c
@@ -386,21 +386,21 @@ static void r600_reallocate_texture_inplace(struct r600_common_context *rctx,
if (!new_tex)
return;
/* Copy the pixels to the new texture. */
if (!invalidate_storage) {
for (i = 0; i <= templ.last_level; i++) {
struct pipe_box box;
u_box_3d(0, 0, 0,
u_minify(templ.width0, i), u_minify(templ.height0, i),
- util_max_layer(&templ, i) + 1, &box);
+ util_num_layers(&templ, i), &box);
rctx->dma_copy(&rctx->b, &new_tex->resource.b.b, i, 0, 0, 0,
&rtex->resource.b.b, i, &box);
}
}
if (new_bind_flag == PIPE_BIND_LINEAR) {
r600_texture_discard_cmask(rctx->screen, rtex);
}
@@ -669,21 +669,21 @@ void r600_texture_get_cmask_info(struct r600_common_screen *rscreen,
unsigned base_align = num_pipes * pipe_interleave_bytes;
unsigned slice_bytes =
((pitch_elements * height * element_bits + 7) / 8) / cmask_tile_elements;
assert(macro_tile_width % 128 == 0);
assert(macro_tile_height % 128 == 0);
out->slice_tile_max = ((pitch_elements * height) / (128*128)) - 1;
out->alignment = MAX2(256, base_align);
- out->size = (util_max_layer(&rtex->resource.b.b, 0) + 1) *
+ out->size = util_num_layers(&rtex->resource.b.b, 0) *
align(slice_bytes, base_align);
}
static void r600_texture_allocate_cmask(struct r600_common_screen *rscreen,
struct r600_texture *rtex)
{
r600_texture_get_cmask_info(rscreen, rtex, &rtex->cmask);
rtex->cmask.offset = align64(rtex->size, rtex->cmask.alignment);
rtex->size = rtex->cmask.offset + rtex->cmask.size;
@@ -778,21 +778,21 @@ static void r600_texture_get_htile_size(struct r600_common_screen *rscreen,
height = align(rtex->resource.b.b.height0, cl_height * 8);
slice_elements = (width * height) / (8 * 8);
slice_bytes = slice_elements * 4;
pipe_interleave_bytes = rscreen->info.pipe_interleave_bytes;
base_align = num_pipes * pipe_interleave_bytes;
rtex->surface.htile_alignment = base_align;
rtex->surface.htile_size =
- (util_max_layer(&rtex->resource.b.b, 0) + 1) *
+ util_num_layers(&rtex->resource.b.b, 0) *
align(slice_bytes, base_align);
}
static void r600_texture_allocate_htile(struct r600_common_screen *rscreen,
struct r600_texture *rtex)
{
r600_texture_get_htile_size(rscreen, rtex);
if (!rtex->surface.htile_size)
return;
@@ -989,21 +989,21 @@ r600_texture_create_object(struct pipe_screen *screen,
}
/* Initialize the CMASK base register value. */
rtex->cmask.base_address_reg =
(rtex->resource.gpu_address + rtex->cmask.offset) >> 8;
if (rscreen->debug_flags & DBG_VM) {
fprintf(stderr, "VM start=0x%"PRIX64" end=0x%"PRIX64" | Texture %ix%ix%i, %i levels, %i samples, %s\n",
rtex->resource.gpu_address,
rtex->resource.gpu_address + rtex->resource.buf->size,
- base->width0, base->height0, util_max_layer(base, 0)+1, base->last_level+1,
+ base->width0, base->height0, util_num_layers(base, 0), base->last_level+1,
base->nr_samples ? base->nr_samples : 1, util_format_short_name(base->format));
}
if (rscreen->debug_flags & DBG_TEX) {
puts("Texture:");
struct u_log_context log;
u_log_context_init(&log);
r600_print_texture_info(rscreen, rtex, &log);
u_log_new_page_print(&log, stdout);
fflush(stdout);
diff --git a/src/gallium/drivers/radeon/r600_texture.c b/src/gallium/drivers/radeon/r600_texture.c
index cb69398..710a571 100644
--- a/src/gallium/drivers/radeon/r600_texture.c
+++ b/src/gallium/drivers/radeon/r600_texture.c
@@ -506,21 +506,21 @@ static void r600_reallocate_texture_inplace(struct r600_common_context *rctx,
if (!new_tex)
return;
/* Copy the pixels to the new texture. */
if (!invalidate_storage) {
for (i = 0; i <= templ.last_level; i++) {
struct pipe_box box;
u_box_3d(0, 0, 0,
u_minify(templ.width0, i), u_minify(templ.height0, i),
- util_max_layer(&templ, i) + 1, &box);
+ util_num_layers(&templ, i), &box);
rctx->dma_copy(&rctx->b, &new_tex->resource.b.b, i, 0, 0, 0,
&rtex->resource.b.b, i, &box);
}
}
if (new_bind_flag == PIPE_BIND_LINEAR) {
r600_texture_discard_cmask(rctx->screen, rtex);
r600_texture_discard_dcc(rctx->screen, rtex);
}
@@ -928,21 +928,21 @@ void si_texture_get_cmask_info(struct si_screen *sscreen,
unsigned slice_elements = (width * height) / (8*8);
/* Each element of CMASK is a nibble. */
unsigned slice_bytes = slice_elements / 2;
out->slice_tile_max = (width * height) / (128*128);
if (out->slice_tile_max)
out->slice_tile_max -= 1;
out->alignment = MAX2(256, base_align);
- out->size = (util_max_layer(&rtex->resource.b.b, 0) + 1) *
+ out->size = util_num_layers(&rtex->resource.b.b, 0) *
align(slice_bytes, base_align);
}
static void r600_texture_allocate_cmask(struct si_screen *sscreen,
struct r600_texture *rtex)
{
si_texture_get_cmask_info(sscreen, rtex, &rtex->cmask);
rtex->cmask.offset = align64(rtex->size, rtex->cmask.alignment);
rtex->size = rtex->cmask.offset + rtex->cmask.size;
@@ -1007,21 +1007,21 @@ static void r600_texture_get_htile_size(struct si_screen *sscreen,
height = align(rtex->resource.b.b.height0, cl_height * 8);
slice_elements = (width * height) / (8 * 8);
slice_bytes = slice_elements * 4;
pipe_interleave_bytes = sscreen->info.pipe_interleave_bytes;
base_align = num_pipes * pipe_interleave_bytes;
rtex->surface.htile_alignment = base_align;
rtex->surface.htile_size =
- (util_max_layer(&rtex->resource.b.b, 0) + 1) *
+ util_num_layers(&rtex->resource.b.b, 0) *
align(slice_bytes, base_align);
}
static void r600_texture_allocate_htile(struct si_screen *sscreen,
struct r600_texture *rtex)
{
if (sscreen->info.chip_class <= VI && !rtex->tc_compatible_htile)
r600_texture_get_htile_size(sscreen, rtex);
if (!rtex->surface.htile_size)
@@ -1326,21 +1326,21 @@ r600_texture_create_object(struct pipe_screen *screen,
}
/* Initialize the CMASK base register value. */
rtex->cmask.base_address_reg =
(rtex->resource.gpu_address + rtex->cmask.offset) >> 8;
if (sscreen->debug_flags & DBG(VM)) {
fprintf(stderr, "VM start=0x%"PRIX64" end=0x%"PRIX64" | Texture %ix%ix%i, %i levels, %i samples, %s\n",
rtex->resource.gpu_address,
rtex->resource.gpu_address + rtex->resource.buf->size,
- base->width0, base->height0, util_max_layer(base, 0)+1, base->last_level+1,
+ base->width0, base->height0, util_num_layers(base, 0), base->last_level+1,
base->nr_samples ? base->nr_samples : 1, util_format_short_name(base->format));
}
if (sscreen->debug_flags & DBG(TEX)) {
puts("Texture:");
struct u_log_context log;
u_log_context_init(&log);
si_print_texture_info(sscreen, rtex, &log);
u_log_new_page_print(&log, stdout);
fflush(stdout);
diff --git a/src/gallium/drivers/radeonsi/si_clear.c b/src/gallium/drivers/radeonsi/si_clear.c
index ba95ed5..0ac83f4 100644
--- a/src/gallium/drivers/radeonsi/si_clear.c
+++ b/src/gallium/drivers/radeonsi/si_clear.c
@@ -207,21 +207,21 @@ void vi_dcc_clear_level(struct si_context *sctx,
dcc_offset = rtex->dcc_offset;
}
if (sctx->b.chip_class >= GFX9) {
/* Mipmap level clears aren't implemented. */
assert(rtex->resource.b.b.last_level == 0);
/* MSAA needs a different clear size. */
assert(rtex->resource.b.b.nr_samples <= 1);
clear_size = rtex->surface.dcc_size;
} else {
- unsigned num_layers = util_max_layer(&rtex->resource.b.b, level) + 1;
+ unsigned num_layers = util_num_layers(&rtex->resource.b.b, level);
/* If this is 0, fast clear isn't possible. (can occur with MSAA) */
assert(rtex->surface.u.legacy.level[level].dcc_fast_clear_size);
/* Layered MSAA DCC fast clears need to clear dcc_fast_clear_size
* bytes for each layer. This is not currently implemented, and
* therefore MSAA DCC isn't even enabled with multiple layers.
*/
assert(rtex->resource.b.b.nr_samples <= 1 || num_layers == 1);
dcc_offset += rtex->surface.u.legacy.level[level].dcc_offset;
diff --git a/src/gallium/drivers/rbug/rbug_core.c b/src/gallium/drivers/rbug/rbug_core.c
index 8eb39c1..7639403 100644
--- a/src/gallium/drivers/rbug/rbug_core.c
+++ b/src/gallium/drivers/rbug/rbug_core.c
@@ -214,21 +214,21 @@ rbug_texture_info(struct rbug_rbug *tr_rbug, struct rbug_header *header, uint32_
break;
tr_tex = NULL;
}
if (!tr_tex) {
mtx_unlock(&rb_screen->list_mutex);
return -ESRCH;
}
t = tr_tex->resource;
- num_layers = util_max_layer(t, 0) + 1;
+ num_layers = util_num_layers(t, 0);
rbug_send_texture_info_reply(tr_rbug->con, serial,
t->target, t->format,
&t->width0, 1,
&t->height0, 1,
&num_layers, 1,
util_format_get_blockwidth(t->format),
util_format_get_blockheight(t->format),
util_format_get_blocksize(t->format),
t->last_level,
--
2.7.4
More information about the mesa-dev
mailing list