[Mesa-dev] [PATCH v2 1/5] i965: define astx5x5 workaround infrastructure

[kevin.rogovin at intel.com]

From: Kevin Rogovin <kevin.rogovin at intel.com>

Signed-off-by: Kevin Rogovin <kevin.rogovin at intel.com>
---
 src/mesa/drivers/dri/i965/Makefile.sources    |  1 +
 src/mesa/drivers/dri/i965/brw_context.c       |  6 +++++
 src/mesa/drivers/dri/i965/brw_context.h       | 24 ++++++++++++++++++
 src/mesa/drivers/dri/i965/gen9_astc5x5_wa.c   | 36 +++++++++++++++++++++++++++
 src/mesa/drivers/dri/i965/intel_batchbuffer.c |  1 +
 src/mesa/drivers/dri/i965/meson.build         |  1 +
 6 files changed, 69 insertions(+)
 create mode 100644 src/mesa/drivers/dri/i965/gen9_astc5x5_wa.c

diff --git a/src/mesa/drivers/dri/i965/Makefile.sources b/src/mesa/drivers/dri/i965/Makefile.sources
index d928f71..4698fcb 100644
--- a/src/mesa/drivers/dri/i965/Makefile.sources
+++ b/src/mesa/drivers/dri/i965/Makefile.sources
@@ -77,6 +77,7 @@ i965_FILES = \
 	gen7_urb.c \
 	gen8_depth_state.c \
 	gen8_multisample_state.c \
+        gen9_astc5x5_wa.c \
 	hsw_queryobj.c \
 	hsw_sol.c \
 	intel_batchbuffer.c \
diff --git a/src/mesa/drivers/dri/i965/brw_context.c b/src/mesa/drivers/dri/i965/brw_context.c
index 126c187..f3ccbda 100644
--- a/src/mesa/drivers/dri/i965/brw_context.c
+++ b/src/mesa/drivers/dri/i965/brw_context.c
@@ -1073,6 +1073,12 @@ brwCreateContext(gl_api api,
    if (ctx->Extensions.INTEL_performance_query)
       brw_init_performance_queries(brw);
 
+   brw->astc5x5_wa.required = (devinfo->gen == 9);
+   brw->astc5x5_wa.mode = BRW_ASTC5x5_WA_MODE_NONE;
+   brw->astc5x5_wa.texture_astc5x5_present = false;
+   brw->astc5x5_wa.texture_with_auxilary_present = false;
+   brw->astc5x5_wa.blorp_sampling_from_astc5x5 = false;
+
    vbo_use_buffer_objects(ctx);
    vbo_always_unmap_buffers(ctx);
 
diff --git a/src/mesa/drivers/dri/i965/brw_context.h b/src/mesa/drivers/dri/i965/brw_context.h
index 0f0aad8..60a1d3b 100644
--- a/src/mesa/drivers/dri/i965/brw_context.h
+++ b/src/mesa/drivers/dri/i965/brw_context.h
@@ -166,6 +166,12 @@ enum brw_cache_id {
    BRW_MAX_CACHE
 };
 
+enum brw_astc5x5_wa_mode_t {
+   BRW_ASTC5x5_WA_MODE_NONE,
+   BRW_ASTC5x5_WA_MODE_HAS_ASTC5x5,
+   BRW_ASTC5x5_WA_MODE_HAS_AUX,
+};
+
 enum brw_state_id {
    /* brw_cache_ids must come first - see brw_program_cache.c */
    BRW_STATE_URB_FENCE = BRW_MAX_CACHE,
@@ -1263,6 +1269,19 @@ struct brw_context
     */
    bool draw_aux_buffer_disabled[MAX_DRAW_BUFFERS];
 
+   /* Certain GEN's have a hardware bug where the sampler hangs if it attempts
+    * to access auxilary buffers and an ASTC5x5 compressed buffer. The workaround
+    * is to make sure that the texture cache is cleared between such accesses
+    * and that such accesses have a command streamer stall between them.
+    */
+   struct {
+      bool required;
+      enum brw_astc5x5_wa_mode_t mode;
+      bool texture_astc5x5_present;
+      bool texture_with_auxilary_present;
+      bool blorp_sampling_from_astc5x5;
+   } astc5x5_wa;
+
    __DRIcontext *driContext;
    struct intel_screen *screen;
 };
@@ -1695,6 +1714,11 @@ void brw_query_internal_format(struct gl_context *ctx, GLenum target,
                                GLenum internalFormat, GLenum pname,
                                GLint *params);
 
+/* gen9_astc5x5_wa.c */
+void gen9_set_astc5x5_wa_mode(struct brw_context *brw,
+                             enum brw_astc5x5_wa_mode_t mode);
+void gen9_astc5x5_perform_wa(struct brw_context *brw);
+
 #ifdef __cplusplus
 }
 #endif
diff --git a/src/mesa/drivers/dri/i965/gen9_astc5x5_wa.c b/src/mesa/drivers/dri/i965/gen9_astc5x5_wa.c
new file mode 100644
index 0000000..247fd00
--- /dev/null
+++ b/src/mesa/drivers/dri/i965/gen9_astc5x5_wa.c
@@ -0,0 +1,36 @@
+#include "brw_context.h"
+#include "brw_defines.h"
+#include "intel_mipmap_tree.h"
+
+void
+gen9_set_astc5x5_wa_mode(struct brw_context *brw,
+                        enum brw_astc5x5_wa_mode_t mode)
+{
+   if (!brw->astc5x5_wa.required ||
+       mode == BRW_ASTC5x5_WA_MODE_NONE ||
+       brw->astc5x5_wa.mode == mode) {
+      return;
+   }
+
+   if (brw->astc5x5_wa.mode != BRW_ASTC5x5_WA_MODE_NONE) {
+      const uint32_t flags = PIPE_CONTROL_CS_STALL |
+         PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE;
+      brw_emit_pipe_control_flush(brw, flags);
+   }
+
+   brw->astc5x5_wa.mode = mode;
+}
+
+void
+gen9_astc5x5_perform_wa(struct brw_context *brw)
+{
+   if (!brw->astc5x5_wa.required) {
+      return;
+   }
+
+   if (brw->astc5x5_wa.texture_astc5x5_present) {
+      gen9_set_astc5x5_wa_mode(brw, BRW_ASTC5x5_WA_MODE_HAS_ASTC5x5);
+   } else if (brw->astc5x5_wa.texture_with_auxilary_present) {
+      gen9_set_astc5x5_wa_mode(brw, BRW_ASTC5x5_WA_MODE_HAS_AUX);
+   }
+}
diff --git a/src/mesa/drivers/dri/i965/intel_batchbuffer.c b/src/mesa/drivers/dri/i965/intel_batchbuffer.c
index 91a6506..b7e2450 100644
--- a/src/mesa/drivers/dri/i965/intel_batchbuffer.c
+++ b/src/mesa/drivers/dri/i965/intel_batchbuffer.c
@@ -613,6 +613,7 @@ brw_new_batch(struct brw_context *brw)
 
    /* Create a new batchbuffer and reset the associated state: */
    intel_batchbuffer_reset_and_clear_render_cache(brw);
+   brw->astc5x5_wa.mode = BRW_ASTC5x5_WA_MODE_NONE;
 
    /* If the kernel supports hardware contexts, then most hardware state is
     * preserved between batches; we only need to re-emit state that is required
diff --git a/src/mesa/drivers/dri/i965/meson.build b/src/mesa/drivers/dri/i965/meson.build
index 0a214a0..3f46f0d 100644
--- a/src/mesa/drivers/dri/i965/meson.build
+++ b/src/mesa/drivers/dri/i965/meson.build
@@ -96,6 +96,7 @@ files_i965 = files(
   'gen7_urb.c',
   'gen8_depth_state.c',
   'gen8_multisample_state.c',
+  'gen9_astc5x5_wa.c',
   'hsw_queryobj.c',
   'hsw_sol.c',
   'intel_batchbuffer.c',
-- 
2.7.4