[Mesa-dev] [PATCH] i965: Combine {VS, FS}_OPCODE_GET_BUFFER_SIZE opcodes.

Jason Ekstrand jason at jlekstrand.net
Sat Dec 30 14:07:49 UTC 2017


Rb


On December 29, 2017 23:39:21 Kenneth Graunke <kenneth at whitecape.org> wrote:

> These are the same, we don't need a separate opcode enum per backend.
> ---
>  src/intel/compiler/brw_eu_defines.h       | 5 ++---
>  src/intel/compiler/brw_fs.cpp             | 2 +-
>  src/intel/compiler/brw_fs_generator.cpp   | 2 +-
>  src/intel/compiler/brw_fs_nir.cpp         | 2 +-
>  src/intel/compiler/brw_shader.cpp         | 9 +++------
>  src/intel/compiler/brw_vec4.cpp           | 2 +-
>  src/intel/compiler/brw_vec4_generator.cpp | 9 ++++-----
>  src/intel/compiler/brw_vec4_nir.cpp       | 2 +-
>  8 files changed, 14 insertions(+), 19 deletions(-)
>
> diff --git a/src/intel/compiler/brw_eu_defines.h 
> b/src/intel/compiler/brw_eu_defines.h
> index 8ed97912b4d..30e2e8f0708 100644
> --- a/src/intel/compiler/brw_eu_defines.h
> +++ b/src/intel/compiler/brw_eu_defines.h
> @@ -451,6 +451,8 @@ enum opcode {
>      */
>     SHADER_OPCODE_BROADCAST,
>
> +   SHADER_OPCODE_GET_BUFFER_SIZE,
> +
>     VEC4_OPCODE_MOV_BYTES,
>     VEC4_OPCODE_PACK_BYTES,
>     VEC4_OPCODE_UNPACK_UNIFORM,
> @@ -479,7 +481,6 @@ enum opcode {
>     FS_OPCODE_VARYING_PULL_CONSTANT_LOAD_GEN4,
>     FS_OPCODE_VARYING_PULL_CONSTANT_LOAD_GEN7,
>     FS_OPCODE_VARYING_PULL_CONSTANT_LOAD_LOGICAL,
> -   FS_OPCODE_GET_BUFFER_SIZE,
>     FS_OPCODE_MOV_DISPATCH_TO_FLAGS,
>     FS_OPCODE_DISCARD_JUMP,
>     FS_OPCODE_SET_SAMPLE_ID,
> @@ -496,8 +497,6 @@ enum opcode {
>     VS_OPCODE_PULL_CONSTANT_LOAD_GEN7,
>     VS_OPCODE_SET_SIMD4X2_HEADER_GEN9,
>
> -   VS_OPCODE_GET_BUFFER_SIZE,
> -
>     VS_OPCODE_UNPACK_FLAGS_SIMD4X2,
>
>     /**
> diff --git a/src/intel/compiler/brw_fs.cpp b/src/intel/compiler/brw_fs.cpp
> index 6d9f0eccb29..9d0546e5797 100644
> --- a/src/intel/compiler/brw_fs.cpp
> +++ b/src/intel/compiler/brw_fs.cpp
> @@ -5007,7 +5007,7 @@ get_lowered_simd_width(const struct gen_device_info 
> *devinfo,
>        return MIN2(8, inst->exec_size);
>
>     case FS_OPCODE_LINTERP:
> -   case FS_OPCODE_GET_BUFFER_SIZE:
> +   case SHADER_OPCODE_GET_BUFFER_SIZE:
>     case FS_OPCODE_DDX_COARSE:
>     case FS_OPCODE_DDX_FINE:
>     case FS_OPCODE_DDY_COARSE:
> diff --git a/src/intel/compiler/brw_fs_generator.cpp 
> b/src/intel/compiler/brw_fs_generator.cpp
> index 6a3b2dcf8a3..37b8f07769e 100644
> --- a/src/intel/compiler/brw_fs_generator.cpp
> +++ b/src/intel/compiler/brw_fs_generator.cpp
> @@ -1964,7 +1964,7 @@ fs_generator::generate_code(const cfg_t *cfg, int 
> dispatch_width)
>           src[0].subnr = 4 * type_sz(src[0].type);
>           brw_MOV(p, dst, stride(src[0], 8, 4, 1));
>           break;
> -      case FS_OPCODE_GET_BUFFER_SIZE:
> +      case SHADER_OPCODE_GET_BUFFER_SIZE:
>           generate_get_buffer_size(inst, dst, src[0], src[1]);
>           break;
>        case SHADER_OPCODE_TEX:
> diff --git a/src/intel/compiler/brw_fs_nir.cpp 
> b/src/intel/compiler/brw_fs_nir.cpp
> index 01651dda444..ab132f700a3 100644
> --- a/src/intel/compiler/brw_fs_nir.cpp
> +++ b/src/intel/compiler/brw_fs_nir.cpp
> @@ -4290,7 +4290,7 @@ fs_visitor::nir_emit_intrinsic(const fs_builder &bld, 
> nir_intrinsic_instr *instr
>        ubld.MOV(src_payload, brw_imm_d(0));
>
>        const unsigned index = prog_data->binding_table.ssbo_start + ssbo_index;
> -      fs_inst *inst = ubld.emit(FS_OPCODE_GET_BUFFER_SIZE, ret_payload,
> +      fs_inst *inst = ubld.emit(SHADER_OPCODE_GET_BUFFER_SIZE, ret_payload,
>                                  src_payload, brw_imm_ud(index));
>        inst->header_size = 0;
>        inst->mlen = 1;
> diff --git a/src/intel/compiler/brw_shader.cpp 
> b/src/intel/compiler/brw_shader.cpp
> index 74b52976d74..1df4f35cd8e 100644
> --- a/src/intel/compiler/brw_shader.cpp
> +++ b/src/intel/compiler/brw_shader.cpp
> @@ -331,6 +331,9 @@ brw_instruction_name(const struct gen_device_info 
> *devinfo, enum opcode op)
>     case SHADER_OPCODE_BROADCAST:
>        return "broadcast";
>
> +   case SHADER_OPCODE_GET_BUFFER_SIZE:
> +      return "get_buffer_size";
> +
>     case VEC4_OPCODE_MOV_BYTES:
>        return "mov_bytes";
>     case VEC4_OPCODE_PACK_BYTES:
> @@ -373,9 +376,6 @@ brw_instruction_name(const struct gen_device_info 
> *devinfo, enum opcode op)
>     case FS_OPCODE_PIXEL_Y:
>        return "pixel_y";
>
> -   case FS_OPCODE_GET_BUFFER_SIZE:
> -      return "fs_get_buffer_size";
> -
>     case FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD:
>        return "uniform_pull_const";
>     case FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD_GEN7:
> @@ -422,9 +422,6 @@ brw_instruction_name(const struct gen_device_info 
> *devinfo, enum opcode op)
>     case VS_OPCODE_SET_SIMD4X2_HEADER_GEN9:
>        return "set_simd4x2_header_gen9";
>
> -   case VS_OPCODE_GET_BUFFER_SIZE:
> -      return "vs_get_buffer_size";
> -
>     case VS_OPCODE_UNPACK_FLAGS_SIMD4X2:
>        return "unpack_flags_simd4x2";
>
> diff --git a/src/intel/compiler/brw_vec4.cpp b/src/intel/compiler/brw_vec4.cpp
> index 73c40ad6009..3ddbe6c57fc 100644
> --- a/src/intel/compiler/brw_vec4.cpp
> +++ b/src/intel/compiler/brw_vec4.cpp
> @@ -361,7 +361,7 @@ vec4_visitor::implied_mrf_writes(vec4_instruction *inst)
>     case SHADER_OPCODE_TG4:
>     case SHADER_OPCODE_TG4_OFFSET:
>     case SHADER_OPCODE_SAMPLEINFO:
> -   case VS_OPCODE_GET_BUFFER_SIZE:
> +   case SHADER_OPCODE_GET_BUFFER_SIZE:
>        return inst->header_size;
>     default:
>        unreachable("not reached");
> diff --git a/src/intel/compiler/brw_vec4_generator.cpp 
> b/src/intel/compiler/brw_vec4_generator.cpp
> index 8e11754e021..f5d6ad8e483 100644
> --- a/src/intel/compiler/brw_vec4_generator.cpp
> +++ b/src/intel/compiler/brw_vec4_generator.cpp
> @@ -1773,6 +1773,10 @@ generate_code(struct brw_codegen *p,
>                        inst, dst, src[0], src[1], src[2]);
>           break;
>
> +      case SHADER_OPCODE_GET_BUFFER_SIZE:
> +         generate_get_buffer_size(p, prog_data, inst, dst, src[0], src[1]);
> +         break;
> +
>        case VS_OPCODE_URB_WRITE:
>           generate_vs_urb_write(p, inst);
>           break;
> @@ -1799,11 +1803,6 @@ generate_code(struct brw_codegen *p,
>           generate_set_simd4x2_header_gen9(p, inst, dst);
>           break;
>
> -
> -      case VS_OPCODE_GET_BUFFER_SIZE:
> -         generate_get_buffer_size(p, prog_data, inst, dst, src[0], src[1]);
> -         break;
> -
>        case GS_OPCODE_URB_WRITE:
>           generate_gs_urb_write(p, inst);
>           break;
> diff --git a/src/intel/compiler/brw_vec4_nir.cpp 
> b/src/intel/compiler/brw_vec4_nir.cpp
> index 4ff3ef9927e..7131fa06b4a 100644
> --- a/src/intel/compiler/brw_vec4_nir.cpp
> +++ b/src/intel/compiler/brw_vec4_nir.cpp
> @@ -455,7 +455,7 @@ vec4_visitor::nir_emit_intrinsic(nir_intrinsic_instr 
> *instr)
>           prog_data->base.binding_table.ssbo_start + ssbo_index;
>        dst_reg result_dst = get_nir_dest(instr->dest);
>        vec4_instruction *inst = new(mem_ctx)
> -         vec4_instruction(VS_OPCODE_GET_BUFFER_SIZE, result_dst);
> +         vec4_instruction(SHADER_OPCODE_GET_BUFFER_SIZE, result_dst);
>
>        inst->base_mrf = 2;
>        inst->mlen = 1; /* always at least one */
> --
> 2.15.1
>
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