[Mesa-dev] [PATCH 1/8] radv/amdgpu: Allow submitting 0 command buffers.

[Bas Nieuwenhuizen]

Signed-off-by: Bas Nieuwenhuizen <basni at google.com>
---
 src/amd/vulkan/radv_device.c                  |  7 +++++--
 src/amd/vulkan/radv_radeon_winsys.h           |  1 +
 src/amd/vulkan/radv_wsi.c                     |  3 ++-
 src/amd/vulkan/winsys/amdgpu/radv_amdgpu_cs.c | 12 ++++++++----
 4 files changed, 16 insertions(+), 7 deletions(-)

diff --git a/src/amd/vulkan/radv_device.c b/src/amd/vulkan/radv_device.c
index 16c9c0ed684..64083e4ce0c 100644
--- a/src/amd/vulkan/radv_device.c
+++ b/src/amd/vulkan/radv_device.c
@@ -1450,7 +1450,8 @@ VkResult radv_QueueSubmit(
 			if (queue->device->trace_bo)
 				*queue->device->trace_id_ptr = 0;
 
-			ret = queue->device->ws->cs_submit(ctx, queue->queue_idx, cs_array + j,
+			ret = queue->device->ws->cs_submit(ctx, radv_queue_family_to_ring(queue->queue_family_index),
+							queue->queue_idx, cs_array + j,
 							advance, preamble_cs,
 							(struct radeon_winsys_sem **)pSubmits[i].pWaitSemaphores,
 							b ? pSubmits[i].waitSemaphoreCount : 0,
@@ -1480,7 +1481,9 @@ VkResult radv_QueueSubmit(
 
 	if (fence) {
 		if (!submitCount)
-			ret = queue->device->ws->cs_submit(ctx, queue->queue_idx,
+			ret = queue->device->ws->cs_submit(ctx,
+							   radv_queue_family_to_ring(queue->queue_family_index),
+							   queue->queue_idx,
 							   &queue->device->empty_cs[queue->queue_family_index],
 							   1, NULL, NULL, 0, NULL, 0,
 							   false, base_fence);
diff --git a/src/amd/vulkan/radv_radeon_winsys.h b/src/amd/vulkan/radv_radeon_winsys.h
index bdb14395d0a..79c182007a6 100644
--- a/src/amd/vulkan/radv_radeon_winsys.h
+++ b/src/amd/vulkan/radv_radeon_winsys.h
@@ -302,6 +302,7 @@ struct radeon_winsys {
 	void (*cs_grow)(struct radeon_winsys_cs * cs, size_t min_size);
 
 	int (*cs_submit)(struct radeon_winsys_ctx *ctx,
+			 enum ring_type queue_type,
 			 int queue_index,
 			 struct radeon_winsys_cs **cs_array,
 			 unsigned cs_count,
diff --git a/src/amd/vulkan/radv_wsi.c b/src/amd/vulkan/radv_wsi.c
index 9c9e1bb0a8d..a5a98a60be2 100644
--- a/src/amd/vulkan/radv_wsi.c
+++ b/src/amd/vulkan/radv_wsi.c
@@ -365,7 +365,8 @@ VkResult radv_QueuePresentKHR(
 		RADV_FROM_HANDLE(radv_fence, fence, swapchain->fences[0]);
 		struct radeon_winsys_fence *base_fence = fence->fence;
 		struct radeon_winsys_ctx *ctx = queue->hw_ctx;
-		queue->device->ws->cs_submit(ctx, queue->queue_idx,
+		queue->device->ws->cs_submit(ctx, radv_queue_family_to_ring(queue->queue_family_index),
+					     queue->queue_idx,
 					     &queue->device->empty_cs[queue->queue_family_index],
 					     1, NULL,
 					     (struct radeon_winsys_sem **)pPresentInfo->pWaitSemaphores,
diff --git a/src/amd/vulkan/winsys/amdgpu/radv_amdgpu_cs.c b/src/amd/vulkan/winsys/amdgpu/radv_amdgpu_cs.c
index b58f5db0622..2f2c3e1338f 100644
--- a/src/amd/vulkan/winsys/amdgpu/radv_amdgpu_cs.c
+++ b/src/amd/vulkan/winsys/amdgpu/radv_amdgpu_cs.c
@@ -774,6 +774,7 @@ static int radv_amdgpu_winsys_cs_submit_sysmem(struct radeon_winsys_ctx *_ctx,
 }
 
 static int radv_amdgpu_winsys_cs_submit(struct radeon_winsys_ctx *_ctx,
+					enum ring_type queue_type,
 					int queue_idx,
 					struct radeon_winsys_cs **cs_array,
 					unsigned cs_count,
@@ -785,17 +786,20 @@ static int radv_amdgpu_winsys_cs_submit(struct radeon_winsys_ctx *_ctx,
 					bool can_patch,
 					struct radeon_winsys_fence *_fence)
 {
-	struct radv_amdgpu_cs *cs = radv_amdgpu_cs(cs_array[0]);
 	struct radv_amdgpu_ctx *ctx = radv_amdgpu_ctx(_ctx);
+	unsigned hw_ip = ring_to_hw_ip(queue_type);
 	int ret;
 	int i;
 	
 	for (i = 0; i < wait_sem_count; i++) {
 		amdgpu_semaphore_handle sem = (amdgpu_semaphore_handle)wait_sem[i];
-		amdgpu_cs_wait_semaphore(ctx->ctx, cs->hw_ip, 0, queue_idx,
+		amdgpu_cs_wait_semaphore(ctx->ctx, hw_ip, 0, queue_idx,
 					 sem);
 	}
-	if (!cs->ws->use_ib_bos) {
+	if (!cs_count) {
+		assert(!_fence);
+		ret = 0;
+	} else if (!radv_amdgpu_cs(cs_array[0])->ws->use_ib_bos) {
 		ret = radv_amdgpu_winsys_cs_submit_sysmem(_ctx, queue_idx, cs_array,
 							   cs_count, preamble_cs, _fence);
 	} else if (can_patch && cs_count > AMDGPU_CS_MAX_IBS_PER_SUBMIT && false) {
@@ -808,7 +812,7 @@ static int radv_amdgpu_winsys_cs_submit(struct radeon_winsys_ctx *_ctx,
 
 	for (i = 0; i < signal_sem_count; i++) {
 		amdgpu_semaphore_handle sem = (amdgpu_semaphore_handle)signal_sem[i];
-		amdgpu_cs_signal_semaphore(ctx->ctx, cs->hw_ip, 0, queue_idx,
+		amdgpu_cs_signal_semaphore(ctx->ctx, hw_ip, 0, queue_idx,
 					   sem);
 	}
 	return ret;
-- 
2.11.0