[Mesa-dev] [PATCH 2/2] i965: Get rid of mark_surface_used()
Iago Toral
itoral at igalia.com
Wed Feb 8 07:23:55 UTC 2017
On Tue, 2017-02-07 at 15:03 -0800, Jason Ekstrand wrote:
> The mark_surface_used function exists for a micro-optimization that
> shrinks the binding table if some of the entries are
> unused. However,
> we already create binding tables based on num_textures, num_ubos,
> etc.,
> so the only case where this is actually able to eliminate something
> is
> if the back-end or NIR is able to dead-code something that the GLSL
> compiler couldn't. Also, it only helps if the thing we were able to
> dead-code happened to be at the end of the list.
>
> Binding table space is cheap. On the other hand, this optimization
> costs us over 150 lines of code scattered throughout NIR and all
> layers
> of the back-end compiler that's a pain to maintain. The tiny
> optimization we get isn't worth the effort.
>
> Cc: Kenneth Graunke <kenneth at whitecape.org>
> ---
> src/compiler/nir/nir.c | 1 -
> src/compiler/nir/nir.h | 3 --
> src/compiler/nir/nir_clone.c | 1 -
> src/compiler/nir/nir_instr_set.c | 2 -
> src/compiler/nir/nir_lower_samplers.c | 2 -
> src/intel/vulkan/anv_nir_apply_pipeline_layout.c | 5 ---
> src/mesa/drivers/dri/i965/brw_fs.cpp | 4 --
> src/mesa/drivers/dri/i965/brw_fs_generator.cpp | 11 ------
> src/mesa/drivers/dri/i965/brw_fs_nir.cpp | 47 --------------
> ----------
> src/mesa/drivers/dri/i965/brw_program.h | 4 --
> src/mesa/drivers/dri/i965/brw_shader.cpp | 20 +---------
> src/mesa/drivers/dri/i965/brw_vec4_generator.cpp | 9 -----
> src/mesa/drivers/dri/i965/brw_vec4_nir.cpp | 47 --------------
> ----------
> src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp | 2 -
> 14 files changed, 2 insertions(+), 156 deletions(-)
>
> diff --git a/src/compiler/nir/nir.c b/src/compiler/nir/nir.c
> index 25bfc31..7b3702c 100644
> --- a/src/compiler/nir/nir.c
> +++ b/src/compiler/nir/nir.c
> @@ -532,7 +532,6 @@ nir_tex_instr_create(nir_shader *shader, unsigned
> num_srcs)
> src_init(&instr->src[i].src);
>
> instr->texture_index = 0;
> - instr->texture_array_size = 0;
> instr->texture = NULL;
> instr->sampler_index = 0;
> instr->sampler = NULL;
> diff --git a/src/compiler/nir/nir.h b/src/compiler/nir/nir.h
> index 8bbc41d..2ffa869 100644
> --- a/src/compiler/nir/nir.h
> +++ b/src/compiler/nir/nir.h
> @@ -1161,9 +1161,6 @@ typedef struct {
> */
> unsigned texture_index;
>
> - /** The size of the texture array or 0 if it's not an array */
> - unsigned texture_array_size;
> -
> /** The texture deref
> *
> * If this is null, use texture_index instead.
> diff --git a/src/compiler/nir/nir_clone.c
> b/src/compiler/nir/nir_clone.c
> index a0ba8f7..bcd87f0 100644
> --- a/src/compiler/nir/nir_clone.c
> +++ b/src/compiler/nir/nir_clone.c
> @@ -420,7 +420,6 @@ clone_tex(clone_state *state, const nir_tex_instr
> *tex)
> ntex->texture_index = tex->texture_index;
> if (tex->texture)
> ntex->texture = clone_deref_var(state, tex->texture, &ntex-
> >instr);
> - ntex->texture_array_size = tex->texture_array_size;
>
> ntex->sampler_index = tex->sampler_index;
> if (tex->sampler)
> diff --git a/src/compiler/nir/nir_instr_set.c
> b/src/compiler/nir/nir_instr_set.c
> index 9cb9ed4..5f9cd93 100644
> --- a/src/compiler/nir/nir_instr_set.c
> +++ b/src/compiler/nir/nir_instr_set.c
> @@ -158,7 +158,6 @@ hash_tex(uint32_t hash, const nir_tex_instr
> *instr)
> unsigned component = instr->component;
> hash = HASH(hash, component);
> hash = HASH(hash, instr->texture_index);
> - hash = HASH(hash, instr->texture_array_size);
> hash = HASH(hash, instr->sampler_index);
>
> assert(!instr->texture && !instr->sampler);
> @@ -312,7 +311,6 @@ nir_instrs_equal(const nir_instr *instr1, const
> nir_instr *instr2)
> tex1->is_new_style_shadow != tex2->is_new_style_shadow ||
> tex1->component != tex2->component ||
> tex1->texture_index != tex2->texture_index ||
> - tex1->texture_array_size != tex2->texture_array_size ||
> tex1->sampler_index != tex2->sampler_index) {
> return false;
> }
> diff --git a/src/compiler/nir/nir_lower_samplers.c
> b/src/compiler/nir/nir_lower_samplers.c
> index 9debfb2..e789ce0 100644
> --- a/src/compiler/nir/nir_lower_samplers.c
> +++ b/src/compiler/nir/nir_lower_samplers.c
> @@ -136,8 +136,6 @@ lower_sampler(nir_tex_instr *instr, const struct
> gl_shader_program *shader_progr
> nir_instr_rewrite_src(&instr->instr,
> &instr->src[instr->num_srcs - 1].src,
> nir_src_for_ssa(indirect));
> -
> - instr->texture_array_size = array_elements;
> }
>
> if (location > shader_program->data->NumUniformStorage - 1 ||
> diff --git a/src/intel/vulkan/anv_nir_apply_pipeline_layout.c
> b/src/intel/vulkan/anv_nir_apply_pipeline_layout.c
> index 8846c2e..8aeaad2 100644
> --- a/src/intel/vulkan/anv_nir_apply_pipeline_layout.c
> +++ b/src/intel/vulkan/anv_nir_apply_pipeline_layout.c
> @@ -212,11 +212,6 @@ lower_tex(nir_tex_instr *tex, struct
> apply_pipeline_layout_state *state)
> nir_tex_src_sampler_offset, state);
> }
>
> - /* The backend only ever uses this to mark used surfaces. We
> don't care
> - * about that little optimization so it just needs to be non-
> zero.
> - */
> - tex->texture_array_size = 1;
> -
> cleanup_tex_deref(tex, tex->texture);
> if (tex->sampler)
> cleanup_tex_deref(tex, tex->sampler);
> diff --git a/src/mesa/drivers/dri/i965/brw_fs.cpp
> b/src/mesa/drivers/dri/i965/brw_fs.cpp
> index c348bc7..8a6737c 100644
> --- a/src/mesa/drivers/dri/i965/brw_fs.cpp
> +++ b/src/mesa/drivers/dri/i965/brw_fs.cpp
> @@ -2116,8 +2116,6 @@ fs_visitor::lower_constant_loads()
> inst->src[i].nr = dst.nr;
> inst->src[i].offset = (base & (block_sz - 1)) +
> inst->src[i].offset % 4;
> -
> - brw_mark_surface_used(prog_data, index);
> }
>
> if (inst->opcode == SHADER_OPCODE_MOV_INDIRECT &&
> @@ -2137,8 +2135,6 @@ fs_visitor::lower_constant_loads()
> inst->src[1],
> pull_index * 4);
> inst->remove(block);
> -
> - brw_mark_surface_used(prog_data, index);
> }
> }
> invalidate_live_intervals();
> diff --git a/src/mesa/drivers/dri/i965/brw_fs_generator.cpp
> b/src/mesa/drivers/dri/i965/brw_fs_generator.cpp
> index 26ffbb1..d8ae195 100644
> --- a/src/mesa/drivers/dri/i965/brw_fs_generator.cpp
> +++ b/src/mesa/drivers/dri/i965/brw_fs_generator.cpp
> @@ -239,8 +239,6 @@ fs_generator::fire_fb_write(fs_inst *inst,
> inst->eot,
> last_render_target,
> inst->header_size != 0);
> -
> - brw_mark_surface_used(&prog_data->base, surf_index);
> }
>
> void
> @@ -364,8 +362,6 @@ fs_generator::generate_fb_read(fs_inst *inst,
> struct brw_reg dst,
> gen9_fb_READ(p, dst, payload, surf_index,
> inst->header_size, inst->size_written / REG_SIZE,
> prog_data->persample_dispatch);
> -
> - brw_mark_surface_used(&prog_data->base, surf_index);
> }
>
> void
> @@ -615,8 +611,6 @@ fs_generator::generate_get_buffer_size(fs_inst
> *inst,
> inst->header_size > 0,
> simd_mode,
> BRW_SAMPLER_RETURN_FORMAT_SINT32);
> -
> - brw_mark_surface_used(prog_data, surf_index.ud);
> }
>
> void
> @@ -900,8 +894,6 @@ fs_generator::generate_tex(fs_inst *inst, struct
> brw_reg dst, struct brw_reg src
> inst->header_size != 0,
> simd_mode,
> return_format);
> -
> - brw_mark_surface_used(prog_data, surface +
> base_binding_table_index);
> } else {
> /* Non-const sampler index */
>
> @@ -1513,9 +1505,6 @@ fs_generator::generate_shader_time_add(fs_inst
> *inst,
> brw_shader_time_add(p, payload,
> prog_data->binding_table.shader_time_start);
> brw_pop_insn_state(p);
> -
> - brw_mark_surface_used(prog_data,
> - prog_data-
> >binding_table.shader_time_start);
> }
>
> void
> diff --git a/src/mesa/drivers/dri/i965/brw_fs_nir.cpp
> b/src/mesa/drivers/dri/i965/brw_fs_nir.cpp
> index 5746daa..546db01 100644
> --- a/src/mesa/drivers/dri/i965/brw_fs_nir.cpp
> +++ b/src/mesa/drivers/dri/i965/brw_fs_nir.cpp
> @@ -3000,10 +3000,6 @@ fs_visitor::emit_non_coherent_fb_read(const
> fs_builder &bld, const fs_reg &dst,
> wm_prog_data->binding_table.render_target_read_start -
> wm_prog_data->base.binding_table.texture_start;
>
> - brw_mark_surface_used(
> - bld.shader->stage_prog_data,
> - wm_prog_data->binding_table.render_target_read_start +
> target);
> -
> /* Calculate the fragment coordinates. */
> const fs_reg coords = bld.vgrf(BRW_REGISTER_TYPE_UD, 3);
> bld.MOV(offset(coords, bld, 0), pixel_x);
> @@ -3470,7 +3466,6 @@ fs_visitor::nir_emit_cs_intrinsic(const
> fs_builder &bld,
> cs_prog_data->uses_num_work_groups = true;
>
> fs_reg surf_index = brw_imm_ud(surface);
> - brw_mark_surface_used(prog_data, surface);
>
> /* Read the 3 GLuint components of gl_NumWorkGroups */
> for (unsigned i = 0; i < 3; i++) {
> @@ -3672,9 +3667,6 @@ fs_visitor::nir_emit_intrinsic(const fs_builder
> &bld, nir_intrinsic_instr *instr
>
> /* Assign the result. */
> bld.MOV(retype(dest, BRW_REGISTER_TYPE_UD), tmp);
> -
> - /* Mark the surface as used. */
> - brw_mark_surface_used(stage_prog_data, surface);
> break;
> }
>
> @@ -3898,7 +3890,6 @@ fs_visitor::nir_emit_intrinsic(const fs_builder
> &bld, nir_intrinsic_instr *instr
> const unsigned index = stage_prog_data-
> >binding_table.ubo_start +
> const_index->u32[0];
> surf_index = brw_imm_ud(index);
> - brw_mark_surface_used(prog_data, index);
> } else {
> /* The block index is not a constant. Evaluate the index
> expression
> * per-channel and add the base UBO index; we have to
> select a value
> @@ -3908,13 +3899,6 @@ fs_visitor::nir_emit_intrinsic(const
> fs_builder &bld, nir_intrinsic_instr *instr
> bld.ADD(surf_index, get_nir_src(instr->src[0]),
> brw_imm_ud(stage_prog_data-
> >binding_table.ubo_start));
> surf_index = bld.emit_uniformize(surf_index);
> -
> - /* Assume this may touch any UBO. It would be nice to
> provide
> - * a tighter bound, but the array information is already
> lowered away.
> - */
> - brw_mark_surface_used(prog_data,
> - stage_prog_data-
> >binding_table.ubo_start +
> - nir->info->num_ubos - 1);
> }
>
> nir_const_value *const_offset = nir_src_as_const_value(instr-
> >src[1]);
> @@ -3973,18 +3957,10 @@ fs_visitor::nir_emit_intrinsic(const
> fs_builder &bld, nir_intrinsic_instr *instr
> unsigned index = stage_prog_data->binding_table.ssbo_start
> +
> const_uniform_block->u32[0];
> surf_index = brw_imm_ud(index);
> - brw_mark_surface_used(prog_data, index);
> } else {
> surf_index = vgrf(glsl_type::uint_type);
> bld.ADD(surf_index, get_nir_src(instr->src[0]),
> brw_imm_ud(stage_prog_data-
> >binding_table.ssbo_start));
> -
> - /* Assume this may touch any UBO. It would be nice to
> provide
> - * a tighter bound, but the array information is already
> lowered away.
> - */
> - brw_mark_surface_used(prog_data,
> - stage_prog_data-
> >binding_table.ssbo_start +
> - nir->info->num_ssbos - 1);
> }
>
> fs_reg offset_reg;
> @@ -4016,15 +3992,10 @@ fs_visitor::nir_emit_intrinsic(const
> fs_builder &bld, nir_intrinsic_instr *instr
> unsigned index = stage_prog_data->binding_table.ssbo_start
> +
> const_uniform_block->u32[0];
> surf_index = brw_imm_ud(index);
> - brw_mark_surface_used(prog_data, index);
> } else {
> surf_index = vgrf(glsl_type::uint_type);
> bld.ADD(surf_index, get_nir_src(instr->src[1]),
> brw_imm_ud(stage_prog_data-
> >binding_table.ssbo_start));
> -
> - brw_mark_surface_used(prog_data,
> - stage_prog_data-
> >binding_table.ssbo_start +
> - nir->info->num_ssbos - 1);
> }
>
> /* Value */
> @@ -4184,7 +4155,6 @@ fs_visitor::nir_emit_intrinsic(const fs_builder
> &bld, nir_intrinsic_instr *instr
> inst->size_written = 4 * REG_SIZE;
>
> bld.MOV(retype(dest, ret_payload.type), component(ret_payload,
> 0));
> - brw_mark_surface_used(prog_data, index);
> break;
> }
>
> @@ -4225,18 +4195,10 @@ fs_visitor::nir_emit_ssbo_atomic(const
> fs_builder &bld,
> unsigned surf_index = stage_prog_data-
> >binding_table.ssbo_start +
> const_surface->u32[0];
> surface = brw_imm_ud(surf_index);
> - brw_mark_surface_used(prog_data, surf_index);
> } else {
> surface = vgrf(glsl_type::uint_type);
> bld.ADD(surface, get_nir_src(instr->src[0]),
> brw_imm_ud(stage_prog_data-
> >binding_table.ssbo_start));
> -
> - /* Assume this may touch any SSBO. This is the same we do for
> other
> - * UBO/SSBO accesses with non-constant surface.
> - */
> - brw_mark_surface_used(prog_data,
> - stage_prog_data-
> >binding_table.ssbo_start +
> - nir->info->num_ssbos - 1);
> }
>
> fs_reg offset = get_nir_src(instr->src[1]);
> @@ -4381,15 +4343,6 @@ fs_visitor::nir_emit_texture(const fs_builder
> &bld, nir_tex_instr *instr)
> unreachable("should be lowered");
>
> case nir_tex_src_texture_offset: {
> - /* Figure out the highest possible texture index and mark
> it as used */
> - uint32_t max_used = texture + instr->texture_array_size -
> 1;
> - if (instr->op == nir_texop_tg4 && devinfo->gen < 8) {
> - max_used += stage_prog_data-
> >binding_table.gather_texture_start;
> - } else {
> - max_used += stage_prog_data-
> >binding_table.texture_start;
> - }
> - brw_mark_surface_used(prog_data, max_used);
> -
> /* Emit code to evaluate the actual indexing expression */
> nir_const_value *const_offset =
> nir_src_as_const_value(instr->src[i].src);
> diff --git a/src/mesa/drivers/dri/i965/brw_program.h
> b/src/mesa/drivers/dri/i965/brw_program.h
> index 6eda165..f06b65d 100644
> --- a/src/mesa/drivers/dri/i965/brw_program.h
> +++ b/src/mesa/drivers/dri/i965/brw_program.h
> @@ -51,10 +51,6 @@ bool brw_debug_recompile_sampler_key(struct
> brw_context *brw,
> void brw_add_texrect_params(struct gl_program *prog);
>
> void
> -brw_mark_surface_used(struct brw_stage_prog_data *prog_data,
> - unsigned surf_index);
> -
> -void
> brw_stage_prog_data_free(const void *prog_data);
>
> void
> diff --git a/src/mesa/drivers/dri/i965/brw_shader.cpp
> b/src/mesa/drivers/dri/i965/brw_shader.cpp
> index 738f8f4..b6e0ba85 100644
> --- a/src/mesa/drivers/dri/i965/brw_shader.cpp
> +++ b/src/mesa/drivers/dri/i965/brw_shader.cpp
> @@ -29,16 +29,6 @@
> #include "brw_vec4_tes.h"
> #include "main/uniforms.h"
>
> -extern "C" void
> -brw_mark_surface_used(struct brw_stage_prog_data *prog_data,
> - unsigned surf_index)
> -{
> - assert(surf_index < BRW_MAX_SURFACES);
> -
> - prog_data->binding_table.size_bytes =
> - MAX2(prog_data->binding_table.size_bytes, (surf_index + 1) *
> 4);
> -}
> -
> enum brw_reg_type
> brw_type_for_base_type(const struct glsl_type *type)
> {
> @@ -1155,7 +1145,7 @@ backend_shader::calculate_cfg()
> * unused but also make sure that addition of small offsets to them
> will
> * trigger some of our asserts that surface indices are <
> BRW_MAX_SURFACES.
> */
> -uint32_t
> +void
> brw_assign_common_binding_table_offsets(const struct gen_device_info
This should be in the previous patch.
> *devinfo,
> const struct gl_program
> *prog,
> struct brw_stage_prog_data
> *stage_prog_data,
> @@ -1228,10 +1218,8 @@ brw_assign_common_binding_table_offsets(const
> struct gen_device_info *devinfo,
> stage_prog_data->binding_table.plane_start[2] =
> next_binding_table_offset;
> next_binding_table_offset += num_textures;
>
> - /* prog_data->base.binding_table.size will be set by
> brw_mark_surface_used. */
> -
> assert(next_binding_table_offset <= BRW_MAX_SURFACES);
> - return next_binding_table_offset;
> + stage_prog_data->binding_table.size_bytes =
> next_binding_table_offset * 4;
The return statement should've been removed in the previous patch.
If I understand the change correctly, this, together with the previous
patch, make it so that brw_assign_common_binding_table_offsets()
assigns *all* the remaining binding table entries in all scenarios, so
that's why you can now compute the binding table size here. In other
words, after this series, it is incorrect to add entries to the binding
table *after* calling this function, right? In that case maybe we
should add a comment here to make this a bit more explicit?
If nobody is against the change and with the comments above fixed, this
is:
Reviewed-by: Iago Toral Quiroga <itoral at igalia.com>
> }
>
> static void
> @@ -1278,10 +1266,6 @@ brw_setup_image_uniform_values(gl_shader_stage
> stage,
> setup_vec4_uniform_value(param +
> BRW_IMAGE_PARAM_SWIZZLING_OFFSET,
> (const gl_constant_value *)image_param->swizzling, 2);
> param += BRW_IMAGE_PARAM_SIZE;
> -
> - brw_mark_surface_used(
> - stage_prog_data,
> - stage_prog_data->binding_table.image_start + image_idx);
> }
> }
>
> diff --git a/src/mesa/drivers/dri/i965/brw_vec4_generator.cpp
> b/src/mesa/drivers/dri/i965/brw_vec4_generator.cpp
> index f68baab..bc91b5a 100644
> --- a/src/mesa/drivers/dri/i965/brw_vec4_generator.cpp
> +++ b/src/mesa/drivers/dri/i965/brw_vec4_generator.cpp
> @@ -291,8 +291,6 @@ generate_tex(struct brw_codegen *p,
> inst->header_size != 0,
> BRW_SAMPLER_SIMD_MODE_SIMD4X2,
> return_format);
> -
> - brw_mark_surface_used(&prog_data->base, sampler +
> base_binding_table_index);
> } else {
> /* Non-constant sampler index. */
>
> @@ -1344,8 +1342,6 @@ generate_get_buffer_size(struct brw_codegen *p,
> inst->header_size > 0,
> BRW_SAMPLER_SIMD_MODE_SIMD4X2,
> BRW_SAMPLER_RETURN_FORMAT_SINT32);
> -
> - brw_mark_surface_used(&prog_data->base, surf_index.ud);
> }
>
> static void
> @@ -1372,9 +1368,6 @@ generate_pull_constant_load_gen7(struct
> brw_codegen *p,
> inst->header_size != 0,
> BRW_SAMPLER_SIMD_MODE_SIMD4X2,
> 0);
> -
> - brw_mark_surface_used(&prog_data->base, surf_index.ud);
> -
> } else {
>
> struct brw_reg addr = vec1(retype(brw_address_reg(0),
> BRW_REGISTER_TYPE_UD));
> @@ -1853,8 +1846,6 @@ generate_code(struct brw_codegen *p,
> case SHADER_OPCODE_SHADER_TIME_ADD:
> brw_shader_time_add(p, src[0],
> prog_data-
> >base.binding_table.shader_time_start);
> - brw_mark_surface_used(&prog_data->base,
> - prog_data-
> >base.binding_table.shader_time_start);
> break;
>
> case SHADER_OPCODE_UNTYPED_ATOMIC:
> diff --git a/src/mesa/drivers/dri/i965/brw_vec4_nir.cpp
> b/src/mesa/drivers/dri/i965/brw_vec4_nir.cpp
> index 3d7c5f0..d8801ed 100644
> --- a/src/mesa/drivers/dri/i965/brw_vec4_nir.cpp
> +++ b/src/mesa/drivers/dri/i965/brw_vec4_nir.cpp
> @@ -498,8 +498,6 @@
> vec4_visitor::nir_emit_intrinsic(nir_intrinsic_instr *instr)
> emit(MOV(dst_reg(MRF, param_base, glsl_type::int_type,
> writemask), lod));
>
> emit(inst);
> -
> - brw_mark_surface_used(&prog_data->base, index);
> break;
> }
>
> @@ -514,16 +512,11 @@
> vec4_visitor::nir_emit_intrinsic(nir_intrinsic_instr *instr)
> unsigned index = prog_data->base.binding_table.ssbo_start +
> const_uniform_block->u32[0];
> surf_index = brw_imm_ud(index);
> - brw_mark_surface_used(&prog_data->base, index);
> } else {
> surf_index = src_reg(this, glsl_type::uint_type);
> emit(ADD(dst_reg(surf_index), get_nir_src(instr->src[1],
> 1),
> brw_imm_ud(prog_data-
> >base.binding_table.ssbo_start)));
> surf_index = emit_uniformize(surf_index);
> -
> - brw_mark_surface_used(&prog_data->base,
> - prog_data-
> >base.binding_table.ssbo_start +
> - nir->info->num_ssbos - 1);
> }
>
> /* Offset */
> @@ -676,20 +669,11 @@
> vec4_visitor::nir_emit_intrinsic(nir_intrinsic_instr *instr)
> unsigned index = prog_data->base.binding_table.ssbo_start +
> const_uniform_block->u32[0];
> surf_index = brw_imm_ud(index);
> -
> - brw_mark_surface_used(&prog_data->base, index);
> } else {
> surf_index = src_reg(this, glsl_type::uint_type);
> emit(ADD(dst_reg(surf_index), get_nir_src(instr->src[0],
> 1),
> brw_imm_ud(prog_data-
> >base.binding_table.ssbo_start)));
> surf_index = emit_uniformize(surf_index);
> -
> - /* Assume this may touch any UBO. It would be nice to
> provide
> - * a tighter bound, but the array information is already
> lowered away.
> - */
> - brw_mark_surface_used(&prog_data->base,
> - prog_data-
> >base.binding_table.ssbo_start +
> - nir->info->num_ssbos - 1);
> }
>
> src_reg offset_reg;
> @@ -867,7 +851,6 @@
> vec4_visitor::nir_emit_intrinsic(nir_intrinsic_instr *instr)
> }
>
> bld.MOV(retype(dest, tmp.type), tmp);
> - brw_mark_surface_used(stage_prog_data, surf_index);
> break;
> }
>
> @@ -884,7 +867,6 @@
> vec4_visitor::nir_emit_intrinsic(nir_intrinsic_instr *instr)
> const unsigned index = prog_data-
> >base.binding_table.ubo_start +
> const_block_index->u32[0];
> surf_index = brw_imm_ud(index);
> - brw_mark_surface_used(&prog_data->base, index);
> } else {
> /* The block index is not a constant. Evaluate the index
> expression
> * per-channel and add the base UBO index; we have to
> select a value
> @@ -895,13 +877,6 @@
> vec4_visitor::nir_emit_intrinsic(nir_intrinsic_instr *instr)
> instr-
> >num_components),
> brw_imm_ud(prog_data-
> >base.binding_table.ubo_start)));
> surf_index = emit_uniformize(surf_index);
> -
> - /* Assume this may touch any UBO. It would be nice to
> provide
> - * a tighter bound, but the array information is already
> lowered away.
> - */
> - brw_mark_surface_used(&prog_data->base,
> - prog_data-
> >base.binding_table.ubo_start +
> - nir->info->num_ubos - 1);
> }
>
> src_reg offset_reg;
> @@ -988,18 +963,10 @@ vec4_visitor::nir_emit_ssbo_atomic(int op,
> nir_intrinsic_instr *instr)
> unsigned surf_index = prog_data->base.binding_table.ssbo_start
> +
> const_surface->u32[0];
> surface = brw_imm_ud(surf_index);
> - brw_mark_surface_used(&prog_data->base, surf_index);
> } else {
> surface = src_reg(this, glsl_type::uint_type);
> emit(ADD(dst_reg(surface), get_nir_src(instr->src[0]),
> brw_imm_ud(prog_data-
> >base.binding_table.ssbo_start)));
> -
> - /* Assume this may touch any UBO. This is the same we do for
> other
> - * UBO/SSBO accesses with non-constant surface.
> - */
> - brw_mark_surface_used(&prog_data->base,
> - prog_data->base.binding_table.ssbo_start
> +
> - nir->info->num_ssbos - 1);
> }
>
> src_reg offset = get_nir_src(instr->src[1], 1);
> @@ -2252,20 +2219,6 @@ vec4_visitor::nir_emit_texture(nir_tex_instr
> *instr)
> }
>
> case nir_tex_src_texture_offset: {
> - /* The highest texture which may be used by this operation
> is
> - * the last element of the array. Mark it here, because the
> generator
> - * doesn't have enough information to determine the bound.
> - */
> - uint32_t array_size = instr->texture_array_size;
> - uint32_t max_used = texture + array_size - 1;
> - if (instr->op == nir_texop_tg4) {
> - max_used += prog_data-
> >base.binding_table.gather_texture_start;
> - } else {
> - max_used += prog_data->base.binding_table.texture_start;
> - }
> -
> - brw_mark_surface_used(&prog_data->base, max_used);
> -
> /* Emit code to evaluate the actual indexing expression */
> nir_const_value *const_offset =
> nir_src_as_const_value(instr->src[i].src);
> diff --git a/src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp
> b/src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp
> index f376618..1d79d0f 100644
> --- a/src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp
> +++ b/src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp
> @@ -1749,8 +1749,6 @@ vec4_visitor::emit_pull_constant_load(bblock_t
> *block, vec4_instruction *inst,
> src = byte_offset(src, 16);
> }
>
> - brw_mark_surface_used(&prog_data->base, index);
> -
> if (is_64bit) {
> temp = retype(temp, BRW_REGISTER_TYPE_DF);
> shuffle_64bit_data(orig_temp, src_reg(temp), false, block,
> inst);
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