[Mesa-dev] [PATCH 2/3] radeonsi: remove separate CB/DB_META flush flags

[Marek Olšák]

From: Marek Olšák <marek.olsak at amd.com>

not used separately
---
 src/gallium/drivers/radeonsi/si_cp_dma.c     |  3 +--
 src/gallium/drivers/radeonsi/si_pipe.h       |  7 ++-----
 src/gallium/drivers/radeonsi/si_state_draw.c | 15 +++++----------
 3 files changed, 8 insertions(+), 17 deletions(-)

diff --git a/src/gallium/drivers/radeonsi/si_cp_dma.c b/src/gallium/drivers/radeonsi/si_cp_dma.c
index e198765..540f946 100644
--- a/src/gallium/drivers/radeonsi/si_cp_dma.c
+++ b/src/gallium/drivers/radeonsi/si_cp_dma.c
@@ -110,22 +110,21 @@ static unsigned get_flush_flags(struct si_context *sctx, enum r600_coherency coh
 {
 	switch (coher) {
 	default:
 	case R600_COHERENCY_NONE:
 		return 0;
 	case R600_COHERENCY_SHADER:
 		return SI_CONTEXT_INV_SMEM_L1 |
 		       SI_CONTEXT_INV_VMEM_L1 |
 		       (sctx->b.chip_class == SI ? SI_CONTEXT_INV_GLOBAL_L2 : 0);
 	case R600_COHERENCY_CB_META:
-		return SI_CONTEXT_FLUSH_AND_INV_CB |
-		       SI_CONTEXT_FLUSH_AND_INV_CB_META;
+		return SI_CONTEXT_FLUSH_AND_INV_CB;
 	}
 }
 
 static unsigned get_tc_l2_flag(struct si_context *sctx, enum r600_coherency coher)
 {
 	return coher == R600_COHERENCY_SHADER &&
 	       sctx->b.chip_class >= CIK ? CP_DMA_USE_L2 : 0;
 }
 
 static void si_cp_dma_prepare(struct si_context *sctx, struct pipe_resource *dst,
diff --git a/src/gallium/drivers/radeonsi/si_pipe.h b/src/gallium/drivers/radeonsi/si_pipe.h
index d17d55a..4075d2c 100644
--- a/src/gallium/drivers/radeonsi/si_pipe.h
+++ b/src/gallium/drivers/radeonsi/si_pipe.h
@@ -46,36 +46,33 @@
 #define SI_CONTEXT_INV_ICACHE		(R600_CONTEXT_PRIVATE_FLAG << 0)
 /* SMEM L1, other names: KCACHE, constant cache, DCACHE, data cache */
 #define SI_CONTEXT_INV_SMEM_L1		(R600_CONTEXT_PRIVATE_FLAG << 1)
 /* VMEM L1 can optionally be bypassed (GLC=1). Other names: TC L1 */
 #define SI_CONTEXT_INV_VMEM_L1		(R600_CONTEXT_PRIVATE_FLAG << 2)
 /* Used by everything except CB/DB, can be bypassed (SLC=1). Other names: TC L2 */
 #define SI_CONTEXT_INV_GLOBAL_L2	(R600_CONTEXT_PRIVATE_FLAG << 3)
 /* Write dirty L2 lines back to memory (shader and CP DMA stores), but don't
  * invalidate L2. SI-CIK can't do it, so they will do complete invalidation. */
 #define SI_CONTEXT_WRITEBACK_GLOBAL_L2	(R600_CONTEXT_PRIVATE_FLAG << 4)
+/* gaps */
 /* Framebuffer caches. */
-#define SI_CONTEXT_FLUSH_AND_INV_CB_META (R600_CONTEXT_PRIVATE_FLAG << 5)
-#define SI_CONTEXT_FLUSH_AND_INV_DB_META (R600_CONTEXT_PRIVATE_FLAG << 6)
 #define SI_CONTEXT_FLUSH_AND_INV_DB	(R600_CONTEXT_PRIVATE_FLAG << 7)
 #define SI_CONTEXT_FLUSH_AND_INV_CB	(R600_CONTEXT_PRIVATE_FLAG << 8)
 /* Engine synchronization. */
 #define SI_CONTEXT_VS_PARTIAL_FLUSH	(R600_CONTEXT_PRIVATE_FLAG << 9)
 #define SI_CONTEXT_PS_PARTIAL_FLUSH	(R600_CONTEXT_PRIVATE_FLAG << 10)
 #define SI_CONTEXT_CS_PARTIAL_FLUSH	(R600_CONTEXT_PRIVATE_FLAG << 11)
 #define SI_CONTEXT_VGT_FLUSH		(R600_CONTEXT_PRIVATE_FLAG << 12)
 #define SI_CONTEXT_VGT_STREAMOUT_SYNC	(R600_CONTEXT_PRIVATE_FLAG << 13)
 
 #define SI_CONTEXT_FLUSH_AND_INV_FRAMEBUFFER (SI_CONTEXT_FLUSH_AND_INV_CB | \
-					      SI_CONTEXT_FLUSH_AND_INV_CB_META | \
-					      SI_CONTEXT_FLUSH_AND_INV_DB | \
-					      SI_CONTEXT_FLUSH_AND_INV_DB_META)
+					      SI_CONTEXT_FLUSH_AND_INV_DB)
 
 #define SI_MAX_BORDER_COLORS	4096
 
 struct si_compute;
 struct hash_table;
 struct u_suballocator;
 
 struct si_screen {
 	struct r600_common_screen	b;
 	unsigned			gs_table_depth;
diff --git a/src/gallium/drivers/radeonsi/si_state_draw.c b/src/gallium/drivers/radeonsi/si_state_draw.c
index b6bd3f1..b6cf9a7 100644
--- a/src/gallium/drivers/radeonsi/si_state_draw.c
+++ b/src/gallium/drivers/radeonsi/si_state_draw.c
@@ -773,37 +773,32 @@ void si_emit_cache_flush(struct si_context *sctx)
 			         S_0085F0_CB3_DEST_BASE_ENA(1) |
 			         S_0085F0_CB4_DEST_BASE_ENA(1) |
 			         S_0085F0_CB5_DEST_BASE_ENA(1) |
 			         S_0085F0_CB6_DEST_BASE_ENA(1) |
 			         S_0085F0_CB7_DEST_BASE_ENA(1);
 
 		/* Necessary for DCC */
 		if (rctx->chip_class == VI)
 			r600_gfx_write_event_eop(rctx, V_028A90_FLUSH_AND_INV_CB_DATA_TS,
 						 0, 0, NULL, 0, 0, 0);
+
+		/* Flush CMASK/FMASK/DCC. SURFACE_SYNC will wait for idle. */
+		radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
+		radeon_emit(cs, EVENT_TYPE(V_028A90_FLUSH_AND_INV_CB_META) | EVENT_INDEX(0));
 	}
 	if (rctx->flags & SI_CONTEXT_FLUSH_AND_INV_DB) {
 		cp_coher_cntl |= S_0085F0_DB_ACTION_ENA(1) |
 				 S_0085F0_DB_DEST_BASE_ENA(1);
-	}
 
-	if (rctx->flags & SI_CONTEXT_FLUSH_AND_INV_CB_META) {
-		radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
-		radeon_emit(cs, EVENT_TYPE(V_028A90_FLUSH_AND_INV_CB_META) | EVENT_INDEX(0));
-		/* needed for wait for idle in SURFACE_SYNC */
-		assert(rctx->flags & SI_CONTEXT_FLUSH_AND_INV_CB);
-	}
-	if (rctx->flags & SI_CONTEXT_FLUSH_AND_INV_DB_META) {
+		/* Flush HTILE. SURFACE_SYNC will wait for idle. */
 		radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
 		radeon_emit(cs, EVENT_TYPE(V_028A90_FLUSH_AND_INV_DB_META) | EVENT_INDEX(0));
-		/* needed for wait for idle in SURFACE_SYNC */
-		assert(rctx->flags & SI_CONTEXT_FLUSH_AND_INV_DB);
 	}
 
 	/* Wait for shader engines to go idle.
 	 * VS and PS waits are unnecessary if SURFACE_SYNC is going to wait
 	 * for everything including CB/DB cache flushes.
 	 */
 	if (!(rctx->flags & (SI_CONTEXT_FLUSH_AND_INV_CB |
 			     SI_CONTEXT_FLUSH_AND_INV_DB))) {
 		if (rctx->flags & SI_CONTEXT_PS_PARTIAL_FLUSH) {
 			radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
-- 
2.7.4